net: dsa: mv88e6xxx: use BMCR definitions for serdes control register
The SGMII/1000base-X serdes register set is a clause 22 register set offset at 0x2000 in the PHYXS device. Rather than inventing our own defintions, use those that already exist, and name the register MV88E6390_SGMII_BMCR. Also remove the unused MV88E6390_SGMII_STATUS definitions. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -410,20 +410,18 @@ static int mv88e6390_serdes_power_sgmii(struct mv88e6xxx_chip *chip, u8 lane,
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int err;
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err = mv88e6390_serdes_read(chip, lane, MDIO_MMD_PHYXS,
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MV88E6390_SGMII_CONTROL, &val);
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MV88E6390_SGMII_BMCR, &val);
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if (err)
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return err;
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if (up)
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new_val = val & ~(MV88E6390_SGMII_CONTROL_RESET |
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MV88E6390_SGMII_CONTROL_LOOPBACK |
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MV88E6390_SGMII_CONTROL_PDOWN);
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new_val = val & ~(BMCR_RESET | BMCR_LOOPBACK | BMCR_PDOWN);
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else
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new_val = val | MV88E6390_SGMII_CONTROL_PDOWN;
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new_val = val | BMCR_PDOWN;
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if (val != new_val)
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err = mv88e6390_serdes_write(chip, lane, MDIO_MMD_PHYXS,
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MV88E6390_SGMII_CONTROL, new_val);
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MV88E6390_SGMII_BMCR, new_val);
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return err;
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}
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@ -47,14 +47,7 @@
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#define MV88E6390_PCS_CONTROL_1_PDOWN BIT(11)
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/* 1000BASE-X and SGMII */
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#define MV88E6390_SGMII_CONTROL 0x2000
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#define MV88E6390_SGMII_CONTROL_RESET BIT(15)
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#define MV88E6390_SGMII_CONTROL_LOOPBACK BIT(14)
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#define MV88E6390_SGMII_CONTROL_PDOWN BIT(11)
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#define MV88E6390_SGMII_STATUS 0x2001
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#define MV88E6390_SGMII_STATUS_AN_DONE BIT(5)
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#define MV88E6390_SGMII_STATUS_REMOTE_FAULT BIT(4)
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#define MV88E6390_SGMII_STATUS_LINK BIT(2)
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#define MV88E6390_SGMII_BMCR (0x2000 + MII_BMCR)
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#define MV88E6390_SGMII_INT_ENABLE 0xa001
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#define MV88E6390_SGMII_INT_SPEED_CHANGE BIT(14)
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#define MV88E6390_SGMII_INT_DUPLEX_CHANGE BIT(13)
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