ARM: shmobile: Common shmobile_scu_base in headsmp-scu.S
Update the code in headsmp-scu.S to use a global shmobile_scu_base variable both for convenient SCU base address storage and for the early SCU setup code in shmobile_secondary_vector_scu. With this patch applied r8a7779, sh73a0 and EMEV2 all make use of the global shmobile_scu_base variable. However only sh73a0 makes use of the SCU bring up code in shmobile_secondary_vector_scu. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This commit is contained in:
Magnus Damm
Simon Horman
parent
ec0d84a8d5
commit
4c8228455d
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@ -16,8 +16,8 @@ obj-$(CONFIG_ARCH_EMEV2) += setup-emev2.o clock-emev2.o
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smp-y := platsmp.o headsmp.o
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smp-$(CONFIG_HOTPLUG_CPU) += hotplug.o
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smp-$(CONFIG_ARCH_SH73A0) += smp-sh73a0.o headsmp-scu.o
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smp-$(CONFIG_ARCH_R8A7779) += smp-r8a7779.o
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smp-$(CONFIG_ARCH_EMEV2) += smp-emev2.o
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smp-$(CONFIG_ARCH_R8A7779) += smp-r8a7779.o headsmp-scu.o
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smp-$(CONFIG_ARCH_EMEV2) += smp-emev2.o headsmp-scu.o
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# IRQ objects
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obj-$(CONFIG_ARCH_SH7372) += entry-intc.o
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@ -39,7 +39,8 @@ ENTRY(shmobile_secondary_vector_scu)
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mrc p15, 0, r0, c0, c0, 5 @ read MIPDR
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and r0, r0, #3 @ mask out cpu ID
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lsl r0, r0, #3 @ we will shift by cpu_id * 8 bits
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mov r1, #0xf0000000 @ SCU base address
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ldr r1, =shmobile_scu_base
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ldr r1, [r1] @ SCU base address
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ldr r2, [r1, #8] @ SCU Power Status Register
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mov r3, #3
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bic r2, r2, r3, lsl r0 @ Clear bits of our CPU (Run Mode)
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@ -48,3 +49,8 @@ ENTRY(shmobile_secondary_vector_scu)
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ldr pc, 1f
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1: .long shmobile_invalidate_start - PAGE_OFFSET + PLAT_PHYS_OFFSET
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ENDPROC(shmobile_secondary_vector_scu)
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.text
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.globl shmobile_scu_base
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shmobile_scu_base:
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.space 4
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@ -1,50 +0,0 @@
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/*
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* SMP support for SoC sh73a0
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*
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* Copyright (C) 2012 Bastian Hecht
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <linux/linkage.h>
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#include <linux/init.h>
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#include <asm/memory.h>
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__CPUINIT
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/*
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* Reset vector for secondary CPUs.
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*
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* First we turn on L1 cache coherency for our CPU. Then we jump to
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* shmobile_invalidate_start that invalidates the cache and hands over control
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* to the common ARM startup code.
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* This function will be mapped to address 0 by the SBAR register.
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* A normal branch is out of range here so we need a long jump. We jump to
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* the physical address as the MMU is still turned off.
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*/
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.align 12
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ENTRY(sh73a0_secondary_vector)
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mrc p15, 0, r0, c0, c0, 5 @ read MIPDR
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and r0, r0, #3 @ mask out cpu ID
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lsl r0, r0, #3 @ we will shift by cpu_id * 8 bits
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mov r1, #0xf0000000 @ SCU base address
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ldr r2, [r1, #8] @ SCU Power Status Register
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mov r3, #3
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bic r2, r2, r3, lsl r0 @ Clear bits of our CPU (Run Mode)
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str r2, [r1, #8] @ write back
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ldr pc, 1f
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1: .long shmobile_invalidate_start - PAGE_OFFSET + PLAT_PHYS_OFFSET
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ENDPROC(sh73a0_secondary_vector)
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@ -95,6 +95,7 @@ extern int shmobile_cpu_is_dead(unsigned int cpu);
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static inline int shmobile_cpu_is_dead(unsigned int cpu) { return 1; }
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#endif
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extern void __iomem *shmobile_scu_base;
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extern void shmobile_smp_init_cpus(unsigned int ncores);
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static inline void __init shmobile_init_late(void)
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@ -32,8 +32,6 @@
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#define EMEV2_SCU_BASE 0x1e000000
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static void __iomem *shmobile_scu_base;
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static DEFINE_SPINLOCK(scu_lock);
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static void modify_scu_cpu_psr(unsigned long set, unsigned long clr)
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@ -33,8 +33,6 @@
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#define AVECR IOMEM(0xfe700040)
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#define R8A7779_SCU_BASE IOMEM(0xf0000000)
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static void __iomem *shmobile_scu_base;
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static struct r8a7779_pm_ch r8a7779_ch_cpu1 = {
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.chan_offs = 0x40, /* PWRSR0 .. PWRER0 */
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.chan_bit = 1, /* ARM1 */
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@ -41,8 +41,6 @@
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#define SH73A0_SCU_BASE IOMEM(0xf0000000)
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static void __iomem *shmobile_scu_base;
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#ifdef CONFIG_HAVE_ARM_TWD
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static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, SH73A0_SCU_BASE + 0x600, 29);
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void __init sh73a0_register_twd(void)
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