x86/entry/32: Use %ss segment where required
When re-building the IRET frame we use %eax as an destination %esp,
make sure to then also match the segment for when there is a nonzero
SS base (ESPFIX).
[peterz: Changelog and minor edits]
Fixes: 3c88c692c2
("x86/stackframe/32: Provide consistent pt_regs")
Signed-off-by: Andy Lutomirski <luto@kernel.org>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: stable@kernel.org
This commit is contained in:
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@ -210,6 +210,8 @@
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/*
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/*
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* The high bits of the CS dword (__csh) are used for CS_FROM_*.
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* The high bits of the CS dword (__csh) are used for CS_FROM_*.
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* Clear them in case hardware didn't do this for us.
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* Clear them in case hardware didn't do this for us.
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*
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* Be careful: we may have nonzero SS base due to ESPFIX.
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*/
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*/
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andl $0x0000ffff, 3*4(%esp)
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andl $0x0000ffff, 3*4(%esp)
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@ -263,6 +265,13 @@
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.endm
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.endm
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.macro IRET_FRAME
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.macro IRET_FRAME
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/*
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* We're called with %ds, %es, %fs, and %gs from the interrupted
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* frame, so we shouldn't use them. Also, we may be in ESPFIX
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* mode and therefore have a nonzero SS base and an offset ESP,
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* so any attempt to access the stack needs to use SS. (except for
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* accesses through %esp, which automatically use SS.)
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*/
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testl $CS_FROM_KERNEL, 1*4(%esp)
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testl $CS_FROM_KERNEL, 1*4(%esp)
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jz .Lfinished_frame_\@
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jz .Lfinished_frame_\@
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@ -276,20 +285,20 @@
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movl 5*4(%esp), %eax # (modified) regs->sp
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movl 5*4(%esp), %eax # (modified) regs->sp
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movl 4*4(%esp), %ecx # flags
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movl 4*4(%esp), %ecx # flags
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movl %ecx, -4(%eax)
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movl %ecx, %ss:-1*4(%eax)
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movl 3*4(%esp), %ecx # cs
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movl 3*4(%esp), %ecx # cs
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andl $0x0000ffff, %ecx
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andl $0x0000ffff, %ecx
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movl %ecx, -8(%eax)
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movl %ecx, %ss:-2*4(%eax)
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movl 2*4(%esp), %ecx # ip
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movl 2*4(%esp), %ecx # ip
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movl %ecx, -12(%eax)
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movl %ecx, %ss:-3*4(%eax)
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movl 1*4(%esp), %ecx # eax
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movl 1*4(%esp), %ecx # eax
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movl %ecx, -16(%eax)
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movl %ecx, %ss:-4*4(%eax)
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popl %ecx
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popl %ecx
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lea -16(%eax), %esp
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lea -4*4(%eax), %esp
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popl %eax
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popl %eax
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.Lfinished_frame_\@:
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.Lfinished_frame_\@:
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.endm
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.endm
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