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[ARM] fix cache alignment code in memset.S 

This code is currently disabled, which explains why no one was affected.

Signed-off-by: Nicolas Pitre <nico@marvell.com>
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
This commit is contained in:
Nicolas Pitre 2008-06-11 12:40:13 -04:00 committed by Lennert Buytenhek
parent f76e915473
commit 4c4925c1f4
1 changed files with 1 additions and 1 deletions
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2
arch/arm/lib/memmove.S
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@ -60,6 +60,7 @@ ENTRY(memmove)
CALGN( bcs 2f )
CALGN( adr r4, 6f )
CALGN( subs r2, r2, ip ) @ C is set here
CALGN( rsb ip, ip, #32 )
CALGN( add pc, r4, ip )
PLD( pld [r1, #-4] )
@ -139,7 +140,6 @@ ENTRY(memmove)
blt 14f
CALGN( ands ip, r1, #31 )
CALGN( rsb ip, ip, #32 )
CALGN( sbcnes r4, ip, r2 ) @ C is always set here
CALGN( subcc r2, r2, ip )
CALGN( bcc 15f )