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clk: uniphier: Add audio system and video input clock control for PXs3 

Add clocks for audio subsystem (AIO) and video input subsystem (EXIV) on
UniPhier PXs3 SoC.

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Link: https://lore.kernel.org/r/1634000035-3114-2-git-send-email-hayashi.kunihiko@socionext.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Kunihiko Hayashi 2021-10-12 09:53:51 +09:00 committed by Stephen Boyd
parent dd5e128020
commit 4c4065c7a5
1 changed files with 2 additions and 0 deletions
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2
drivers/clk/uniphier/clk-uniphier-sys.c
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@ -288,6 +288,8 @@ const struct uniphier_clk_data uniphier_pxs3_sys_clk_data[] = {
UNIPHIER_CLK_GATE("sata0", 28, NULL, 0x210c, 7),
UNIPHIER_CLK_GATE("sata1", 29, NULL, 0x210c, 8),
UNIPHIER_CLK_GATE("sata-phy", 30, NULL, 0x210c, 21),
UNIPHIER_LD11_SYS_CLK_AIO(40),
UNIPHIER_LD11_SYS_CLK_EXIV(42),
/* CPU gears */
UNIPHIER_CLK_DIV4("cpll", 2, 3, 4, 8),
UNIPHIER_CLK_DIV4("spll", 2, 3, 4, 8),