sh_eth: add sh_eth_cpu_data::cexcr flag
GEther controllers have CERCR/CEECR instead of CNDCR on the others. Currently we are calling sh_eth_is_gether() in order to check for this, however it would be simpler to check the new 'cexcr' bitfield in the 'struct sh_eth_cpu_data'; then we'd be able to remove sh_eth_is_gether() as there would be no callers left... Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -450,11 +450,6 @@ static u32 sh_eth_tsu_read(struct sh_eth_private *mdp, int enum_index)
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return ioread32(mdp->tsu_addr + mdp->reg_offset[enum_index]);
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}
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static bool sh_eth_is_gether(struct sh_eth_private *mdp)
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{
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return mdp->reg_offset == sh_eth_offset_gigabit;
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}
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static void sh_eth_select_mii(struct net_device *ndev)
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{
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struct sh_eth_private *mdp = netdev_priv(ndev);
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@ -661,6 +656,7 @@ static struct sh_eth_cpu_data r8a7740_data = {
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.tsu = 1,
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.select_mii = 1,
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.magic = 1,
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.cexcr = 1,
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};
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/* There is CPU dependent code */
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@ -918,6 +914,7 @@ static struct sh_eth_cpu_data sh7757_data_giga = {
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.no_ade = 1,
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.xdfar_rw = 1,
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.tsu = 1,
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.cexcr = 1,
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.dual_port = 1,
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};
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@ -959,6 +956,7 @@ static struct sh_eth_cpu_data sh7734_data = {
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.hw_checksum = 1,
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.select_mii = 1,
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.magic = 1,
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.cexcr = 1,
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};
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/* SH7763 */
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@ -997,6 +995,7 @@ static struct sh_eth_cpu_data sh7763_data = {
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.tsu = 1,
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.irq_flags = IRQF_SHARED,
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.magic = 1,
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.cexcr = 1,
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.dual_port = 1,
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};
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@ -2540,7 +2539,7 @@ static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
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sh_eth_update_stat(ndev, &ndev->stats.collisions, CDCR);
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sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, LCCR);
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if (sh_eth_is_gether(mdp)) {
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if (mdp->cd->cexcr) {
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sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
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CERCR);
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sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
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@ -515,6 +515,7 @@ struct sh_eth_cpu_data {
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unsigned rtrate:1; /* EtherC has RTRATE register */
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unsigned magic:1; /* EtherC has ECMR.MPDE and ECSR.MPD */
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unsigned no_tx_cntrs:1; /* EtherC DOES NOT have TX error counters */
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unsigned cexcr:1; /* EtherC has CERCR/CEECR */
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unsigned dual_port:1; /* Dual EtherC/E-DMAC */
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};
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