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staging: iio: resolver: ad2s1210: Fix alignment for DMA safety 

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_DMA_MINALIGN definition.  As the tx[] an rx[] buffers are only used
in the same SPI exchanges, we should be safe with them on the same cacheline.
Hence only mark the first one __aligned(IIO_DMA_MINALIGN).

Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Link: https://lore.kernel.org/r/20220807151218.656881-5-jic23@kernel.org
This commit is contained in:
Jonathan Cameron 2022-08-07 16:12:18 +01:00
parent 48a1319164
commit 4c0babbd97
1 changed files with 2 additions and 2 deletions
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4
drivers/staging/iio/resolver/ad2s1210.c
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@ -94,8 +94,8 @@ struct ad2s1210_state {
bool hysteresis;
u8 resolution;
enum ad2s1210_mode mode;
u8 rx[2] ____cacheline_aligned;
u8 tx[2] ____cacheline_aligned;
u8 rx[2] __aligned(IIO_DMA_MINALIGN);
u8 tx[2];
};
static const int ad2s1210_mode_vals[4][2] = {