Merge branch 'intel-cleanups'
Guangbin Huang says: ==================== net: intel: some cleanups This patchset adds some cleanups for intel e1000/e1000e ethernet driver. ==================== Reviewed-by: Tony Nguyen <anthony.l.nguyen@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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4bebe32407
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@ -2522,7 +2522,7 @@ s32 e1000_check_for_link(struct e1000_hw *hw)
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* turn it on. For compatibility with a TBI link
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* partner, we will store bad packets. Some
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* frames have an additional byte on the end and
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* will look like CRC errors to to the hardware.
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* will look like CRC errors to the hardware.
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*/
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if (!hw->tbi_compatibility_on) {
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hw->tbi_compatibility_on = true;
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@ -2723,7 +2723,7 @@ static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, u32 data, u16 count)
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* e1000_shift_in_mdi_bits - Shifts data bits in from the PHY
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* @hw: Struct containing variables accessed by shared code
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*
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* Bits are shifted in in MSB to LSB order.
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* Bits are shifted in MSB to LSB order.
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*/
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static u16 e1000_shift_in_mdi_bits(struct e1000_hw *hw)
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{
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@ -5245,7 +5245,7 @@ static pci_ers_result_t e1000_io_error_detected(struct pci_dev *pdev,
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if (!test_and_set_bit(__E1000_DISABLED, &adapter->flags))
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pci_disable_device(pdev);
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/* Request a slot slot reset. */
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/* Request a slot reset. */
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return PCI_ERS_RESULT_NEED_RESET;
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}
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@ -4639,7 +4639,7 @@ static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
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* @hw: pointer to the HW structure
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*
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* ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
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* register, so the the bus width is hard coded.
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* register, so the bus width is hard coded.
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**/
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static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
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{
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@ -7118,7 +7118,7 @@ static pci_ers_result_t e1000_io_error_detected(struct pci_dev *pdev,
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pci_disable_device(pdev);
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/* Request a slot slot reset. */
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/* Request a slot reset. */
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return PCI_ERS_RESULT_NEED_RESET;
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}
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@ -2978,7 +2978,7 @@ static u32 e1000_get_phy_addr_for_hv_page(u32 page)
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* @data: pointer to the data to be read or written
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* @read: determines if operation is read or write
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*
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* Reads the PHY register at offset and stores the retreived information
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* Reads the PHY register at offset and stores the retrieved information
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* in data. Assumes semaphore already acquired. Note that the procedure
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* to access these regs uses the address port and data port to read/write.
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* These accesses done with PHY address 2 and without using pages.
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