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Merge branch 'clps711x/soc' into next/soc 

* clps711x/soc:
  ARM: clps711x: merge files related to EDB7211-board into one
  ARM: clps711x: merge all CLPS711X-defconfigs into one
  ARM: clps711x: make all virtual addresses definition via one macro
  ARM: clps711x: added missing definitions
  ARM: clps711x: rework IRQ sybsustem initialization
  ARM: clps711x: p720t: remove missing #include
  ARM: clps711x: convert to clockevents
This commit is contained in:
Arnd Bergmann 2012-10-25 17:23:50 +02:00
parent a0f2a5a184 2a5528912d
commit 4bddddf24b
16 changed files with 223 additions and 290 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm/Kconfig
View File

@ -364,10 +364,10 @@ config ARCH_CNS3XXX
config ARCH_CLPS711X
bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
select ARCH_USES_GETTIMEOFFSET
select CLKDEV_LOOKUP
select COMMON_CLK
select CPU_ARM720T
select GENERIC_CLOCKEVENTS
select NEED_MACH_MEMORY_H
help
Support for Cirrus Logic 711x/721x/731x based boards.

78
arch/arm/configs/clps711x_defconfig Normal file
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@ -0,0 +1,78 @@
CONFIG_EXPERIMENTAL=y
CONFIG_SYSVIPC=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_BLK_DEV_INITRD=y
CONFIG_EMBEDDED=y
CONFIG_PARTITION_ADVANCED=y
# CONFIG_MSDOS_PARTITION is not set
CONFIG_ARCH_CLPS711X=y
CONFIG_ARCH_AUTCPU12=y
CONFIG_ARCH_CDB89712=y
CONFIG_ARCH_CLEP7312=y
CONFIG_ARCH_EDB7211=y
CONFIG_ARCH_P720T=y
CONFIG_ARCH_FORTUNET=y
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
# CONFIG_IPV6 is not set
CONFIG_IRDA=y
CONFIG_IRTTY_SIR=y
CONFIG_EP7211_DONGLE=y
CONFIG_MTD=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI=y
CONFIG_MTD_JEDECPROBE=y
CONFIG_MTD_CFI_INTELEXT=y
CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_CFI_STAA=y
CONFIG_MTD_CDB89712=y
CONFIG_MTD_AUTCPU12=y
CONFIG_MTD_PLATRAM=y
CONFIG_BLK_DEV_RAM=y
CONFIG_NETDEVICES=y
# CONFIG_NET_VENDOR_3COM is not set
# CONFIG_NET_VENDOR_AMD is not set
# CONFIG_NET_VENDOR_BROADCOM is not set
# CONFIG_NET_VENDOR_CHELSIO is not set
CONFIG_CS89x0=y
# CONFIG_NET_VENDOR_FARADAY is not set
# CONFIG_NET_VENDOR_FUJITSU is not set
# CONFIG_NET_VENDOR_HP is not set
# CONFIG_NET_VENDOR_INTEL is not set
# CONFIG_NET_VENDOR_MARVELL is not set
# CONFIG_NET_VENDOR_MICREL is not set
# CONFIG_NET_VENDOR_NATSEMI is not set
# CONFIG_NET_VENDOR_RACAL is not set
# CONFIG_NET_VENDOR_SEEQ is not set
# CONFIG_NET_VENDOR_SMSC is not set
# CONFIG_NET_VENDOR_STMICRO is not set
# CONFIG_NET_VENDOR_WIZNET is not set
# CONFIG_WLAN is not set
# CONFIG_INPUT is not set
# CONFIG_SERIO is not set
# CONFIG_VT is not set
CONFIG_SERIAL_CLPS711X_CONSOLE=y
# CONFIG_HW_RANDOM is not set
# CONFIG_HWMON is not set
CONFIG_FB=y
CONFIG_FB_CLPS711X=y
# CONFIG_USB_SUPPORT is not set
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
# CONFIG_IOMMU_SUPPORT is not set
CONFIG_EXT2_FS=y
CONFIG_MINIX_FS=y
# CONFIG_NETWORK_FILESYSTEMS is not set
# CONFIG_FTRACE is not set
CONFIG_DEBUG_USER=y
CONFIG_DEBUG_LL=y
CONFIG_EARLY_PRINTK=y
# CONFIG_CRYPTO_ANSI_CPRNG is not set
# CONFIG_CRYPTO_HW is not set
# CONFIG_CRC32 is not set

27
arch/arm/configs/edb7211_defconfig
View File

@ -1,27 +0,0 @@
CONFIG_EXPERIMENTAL=y
CONFIG_SYSVIPC=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_BLK_DEV_INITRD=y
CONFIG_EXPERT=y
# CONFIG_HOTPLUG is not set
CONFIG_ARCH_CLPS711X=y
CONFIG_ARCH_EDB7211=y
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
# CONFIG_IPV6 is not set
CONFIG_BLK_DEV_RAM=y
CONFIG_NETDEVICES=y
# CONFIG_INPUT is not set
CONFIG_SERIO_LIBPS2=y
# CONFIG_VT is not set
CONFIG_SERIAL_CLPS711X=y
CONFIG_SERIAL_CLPS711X_CONSOLE=y
CONFIG_EXT2_FS=y
CONFIG_MINIX_FS=y
CONFIG_PARTITION_ADVANCED=y
# CONFIG_MSDOS_PARTITION is not set
CONFIG_DEBUG_USER=y

28
arch/arm/configs/fortunet_defconfig
View File

@ -1,28 +0,0 @@
CONFIG_EXPERIMENTAL=y
CONFIG_SYSVIPC=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_BLK_DEV_INITRD=y
CONFIG_EXPERT=y
# CONFIG_HOTPLUG is not set
CONFIG_ARCH_CLPS711X=y
CONFIG_ARCH_FORTUNET=y
# CONFIG_ARM_THUMB is not set
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_FPE_FASTFPE=y
CONFIG_BINFMT_AOUT=y
CONFIG_NET=y
CONFIG_UNIX=y
CONFIG_MTD=y
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI=y
CONFIG_MTD_CFI_INTELEXT=y
CONFIG_BLK_DEV_RAM=y
# CONFIG_INPUT is not set
# CONFIG_SERIO is not set
# CONFIG_VT is not set
CONFIG_SERIAL_CLPS711X=y
CONFIG_SERIAL_CLPS711X_CONSOLE=y
CONFIG_EXT2_FS=y
CONFIG_DEBUG_USER=y

2
arch/arm/mach-clps711x/Makefile
View File

@ -12,6 +12,6 @@ obj- :=
obj-$(CONFIG_ARCH_AUTCPU12) += autcpu12.o
obj-$(CONFIG_ARCH_CDB89712) += cdb89712.o
obj-$(CONFIG_ARCH_CLEP7312) += clep7312.o
obj-$(CONFIG_ARCH_EDB7211) += edb7211-arch.o edb7211-mm.o
obj-$(CONFIG_ARCH_EDB7211) += edb7211.o
obj-$(CONFIG_ARCH_FORTUNET) += fortunet.o
obj-$(CONFIG_ARCH_P720T) += p720t.o

15
arch/arm/mach-clps711x/autcpu12.c
View File

@ -39,19 +39,10 @@
#include "common.h"
/*
* The on-chip registers are given a size of 1MB so that a section can
* be used to map them; this saves a page table. This is the place to
* add mappings for ROM, expansion memory, PCMCIA, etc. (if static
* mappings are chosen for those areas).
*
*/
static struct map_desc autcpu12_io_desc[] __initdata = {
/* memory-mapped extra io and CS8900A Ethernet chip */
/* ethernet chip */
{
.virtual = AUTCPU12_VIRT_CS8900A,
/* Memory-mapped extra io and CS8900A Ethernet chip */
{
.virtual = IO_ADDRESS(AUTCPU12_PHYS_CS8900A),
.pfn = __phys_to_pfn(AUTCPU12_PHYS_CS8900A),
.length = SZ_1M,
.type = MT_DEVICE

4
arch/arm/mach-clps711x/cdb89712.c
View File

@ -40,8 +40,8 @@
*/
static struct map_desc cdb89712_io_desc[] __initdata = {
{
.virtual = ETHER_BASE,
.pfn =__phys_to_pfn(ETHER_START),
.virtual = IO_ADDRESS(ETHER_PHYS_BASE),
.pfn = __phys_to_pfn(ETHER_PHYS_BASE),
.length = ETHER_SIZE,
.type = MT_DEVICE
}

113
arch/arm/mach-clps711x/common.c
View File

@ -21,13 +21,14 @@
*/
#include <linux/io.h>
#include <linux/init.h>
#include <linux/sizes.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/clk.h>
#include <linux/clkdev.h>
#include <linux/clockchips.h>
#include <linux/clk-provider.h>
#include <asm/sizes.h>
#include <asm/mach/map.h>
#include <asm/mach/time.h>
#include <asm/system_misc.h>
@ -36,7 +37,6 @@
static struct clk *clk_pll, *clk_bus, *clk_uart, *clk_timerl, *clk_timerh,
*clk_tint, *clk_spi;
static unsigned long latch;
/*
* This maps the generic CLPS711x registers
@ -45,7 +45,7 @@ static struct map_desc clps711x_io_desc[] __initdata = {
{
.virtual = (unsigned long)CLPS711X_VIRT_BASE,
.pfn = __phys_to_pfn(CLPS711X_PHYS_BASE),
.length = SZ_1M,
.length = SZ_64K,
.type = MT_DEVICE
}
};
@ -65,6 +65,10 @@ static void int1_mask(struct irq_data *d)
}
static void int1_ack(struct irq_data *d)
{
}
static void int1_eoi(struct irq_data *d)
{
switch (d->irq) {
case IRQ_CSINT: clps_writel(0, COEOI); break;
@ -86,7 +90,9 @@ static void int1_unmask(struct irq_data *d)
}
static struct irq_chip int1_chip = {
.name = "Interrupt Vector 1 ",
.irq_ack = int1_ack,
.irq_eoi = int1_eoi,
.irq_mask = int1_mask,
.irq_unmask = int1_unmask,
};
@ -101,6 +107,10 @@ static void int2_mask(struct irq_data *d)
}
static void int2_ack(struct irq_data *d)
{
}
static void int2_eoi(struct irq_data *d)
{
switch (d->irq) {
case IRQ_KBDINT: clps_writel(0, KBDEOI); break;
@ -117,73 +127,93 @@ static void int2_unmask(struct irq_data *d)
}
static struct irq_chip int2_chip = {
.name = "Interrupt Vector 2 ",
.irq_ack = int2_ack,
.irq_eoi = int2_eoi,
.irq_mask = int2_mask,
.irq_unmask = int2_unmask,
};
struct clps711x_irqdesc {
int nr;
struct irq_chip *chip;
irq_flow_handler_t handle;
};
static struct clps711x_irqdesc clps711x_irqdescs[] __initdata = {
{ IRQ_CSINT, &int1_chip, handle_fasteoi_irq, },
{ IRQ_EINT1, &int1_chip, handle_level_irq, },
{ IRQ_EINT2, &int1_chip, handle_level_irq, },
{ IRQ_EINT3, &int1_chip, handle_level_irq, },
{ IRQ_TC1OI, &int1_chip, handle_fasteoi_irq, },
{ IRQ_TC2OI, &int1_chip, handle_fasteoi_irq, },
{ IRQ_RTCMI, &int1_chip, handle_fasteoi_irq, },
{ IRQ_TINT, &int1_chip, handle_fasteoi_irq, },
{ IRQ_UTXINT1, &int1_chip, handle_level_irq, },
{ IRQ_URXINT1, &int1_chip, handle_level_irq, },
{ IRQ_UMSINT, &int1_chip, handle_fasteoi_irq, },
{ IRQ_SSEOTI, &int1_chip, handle_level_irq, },
{ IRQ_KBDINT, &int2_chip, handle_fasteoi_irq, },
{ IRQ_SS2RX, &int2_chip, handle_level_irq, },
{ IRQ_SS2TX, &int2_chip, handle_level_irq, },
{ IRQ_UTXINT2, &int2_chip, handle_level_irq, },
{ IRQ_URXINT2, &int2_chip, handle_level_irq, },
};
void __init clps711x_init_irq(void)
{
unsigned int i;
for (i = 0; i < NR_IRQS; i++) {
if (INT1_IRQS & (1 << i)) {
irq_set_chip_and_handler(i, &int1_chip,
handle_level_irq);
set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
}
if (INT2_IRQS & (1 << i)) {
irq_set_chip_and_handler(i, &int2_chip,
handle_level_irq);
set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
}
}
/*
* Disable interrupts
*/
/* Disable interrupts */
clps_writel(0, INTMR1);
clps_writel(0, INTMR2);
clps_writel(0, INTMR3);
/*
* Clear down any pending interrupts
*/
/* Clear down any pending interrupts */
clps_writel(0, BLEOI);
clps_writel(0, MCEOI);
clps_writel(0, COEOI);
clps_writel(0, TC1EOI);
clps_writel(0, TC2EOI);
clps_writel(0, RTCEOI);
clps_writel(0, TEOI);
clps_writel(0, UMSEOI);
clps_writel(0, SYNCIO);
clps_writel(0, KBDEOI);
clps_writel(0, SRXEOF);
clps_writel(0xffffffff, DAISR);
for (i = 0; i < ARRAY_SIZE(clps711x_irqdescs); i++) {
irq_set_chip_and_handler(clps711x_irqdescs[i].nr,
clps711x_irqdescs[i].chip,
clps711x_irqdescs[i].handle);
set_irq_flags(clps711x_irqdescs[i].nr,
IRQF_VALID | IRQF_PROBE);
}
}
/*
* gettimeoffset() returns time since last timer tick, in usecs.
*
* 'LATCH' is hwclock ticks (see CLOCK_TICK_RATE in timex.h) per jiffy.
* 'tick' is usecs per jiffy.
*/
static unsigned long clps711x_gettimeoffset(void)
static void clps711x_clockevent_set_mode(enum clock_event_mode mode,
struct clock_event_device *evt)
{
unsigned long hwticks;
hwticks = latch - (clps_readl(TC2D) & 0xffff);
return (hwticks * (tick_nsec / 1000)) / latch;
}
/*
* IRQ handler for the timer
*/
static irqreturn_t p720t_timer_interrupt(int irq, void *dev_id)
static struct clock_event_device clockevent_clps711x = {
.name = "CLPS711x Clockevents",
.rating = 300,
.features = CLOCK_EVT_FEAT_PERIODIC,
.set_mode = clps711x_clockevent_set_mode,
};
static irqreturn_t clps711x_timer_interrupt(int irq, void *dev_id)
{
timer_tick();
clockevent_clps711x.event_handler(&clockevent_clps711x);
return IRQ_HANDLED;
}
static struct irqaction clps711x_timer_irq = {
.name = "CLPS711x Timer Tick",
.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
.handler = p720t_timer_interrupt,
.handler = clps711x_timer_interrupt,
};
static void add_fixed_clk(struct clk *clk, const char *name, int rate)
@ -244,20 +274,19 @@ static void __init clps711x_timer_init(void)
pr_info("CPU frequency set at %i Hz.\n", cpu);
latch = (timh + HZ / 2) / HZ;
clps_writew(DIV_ROUND_CLOSEST(timh, HZ), TC2D);
tmp = clps_readl(SYSCON1);
tmp |= SYSCON1_TC2S | SYSCON1_TC2M;
clps_writel(tmp, SYSCON1);
clps_writel(latch - 1, TC2D);
clockevents_config_and_register(&clockevent_clps711x, timh, 1, 0xffff);
setup_irq(IRQ_TC2OI, &clps711x_timer_irq);
}
struct sys_timer clps711x_timer = {
.init = clps711x_timer_init,
.offset = clps711x_gettimeoffset,
};
void clps711x_restart(char mode, const char *cmd)

82
arch/arm/mach-clps711x/edb7211-mm.c
View File

@ -1,82 +0,0 @@
/*
* linux/arch/arm/mach-clps711x/mm.c
*
* Extra MM routines for the EDB7211 board
*
* Copyright (C) 2000, 2001 Blue Mug, Inc. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/bug.h>
#include <mach/hardware.h>
#include <asm/page.h>
#include <asm/sizes.h>
#include <asm/mach/map.h>
extern void clps711x_map_io(void);
/*
* The on-chip registers are given a size of 1MB so that a section can
* be used to map them; this saves a page table. This is the place to
* add mappings for ROM, expansion memory, PCMCIA, etc. (if static
* mappings are chosen for those areas).
*
* Here is a physical memory map (to be fleshed out later):
*
* Physical Address Size Description
* ----------------- ----- ---------------------------------
* c0000000-c001ffff 128KB reserved for video RAM [1]
* c0020000-c0023fff 16KB parameters (see Documentation/arm/Setup)
* c0024000-c0027fff 16KB swapper_pg_dir (task 0 page directory)
* c0028000-... kernel image (TEXTADDR)
*
* [1] Unused pages should be given back to the VM; they are not yet.
* The parameter block should also be released (not sure if this
* happens).
*/
static struct map_desc edb7211_io_desc[] __initdata = {
{ /* memory-mapped extra keyboard row */
.virtual = EP7211_VIRT_EXTKBD,
.pfn = __phys_to_pfn(EP7211_PHYS_EXTKBD),
.length = SZ_1M,
.type = MT_DEVICE,
}, { /* and CS8900A Ethernet chip */
.virtual = EP7211_VIRT_CS8900A,
.pfn = __phys_to_pfn(EP7211_PHYS_CS8900A),
.length = SZ_1M,
.type = MT_DEVICE,
}, { /* flash banks */
.virtual = EP7211_VIRT_FLASH1,
.pfn = __phys_to_pfn(EP7211_PHYS_FLASH1),
.length = SZ_8M,
.type = MT_DEVICE,
}, {
.virtual = EP7211_VIRT_FLASH2,
.pfn = __phys_to_pfn(EP7211_PHYS_FLASH2),
.length = SZ_8M,
.type = MT_DEVICE,
}
};
void __init edb7211_map_io(void)
{
clps711x_map_io();
iotable_init(edb7211_io_desc, ARRAY_SIZE(edb7211_io_desc));
}

58
arch/arm/mach-clps711x/edb7211-arch.c → arch/arm/mach-clps711x/edb7211.c
View File

@ -1,39 +1,61 @@
/*
* linux/arch/arm/mach-clps711x/arch-edb7211.c
*
* Copyright (C) 2000, 2001 Blue Mug, Inc. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/init.h>
#include <linux/memblock.h>
#include <linux/types.h>
#include <linux/string.h>
#include <asm/setup.h>
#include <asm/mach-types.h>
#include <asm/mach/map.h>
#include <asm/mach/arch.h>
#include <asm/mach-types.h>
#include <mach/hardware.h>
#include "common.h"
extern void edb7211_map_io(void);
#define VIDEORAM_SIZE SZ_128K
static struct map_desc edb7211_io_desc[] __initdata = {
{ /* Memory-mapped extra keyboard row */
.virtual = IO_ADDRESS(EP7211_PHYS_EXTKBD),
.pfn = __phys_to_pfn(EP7211_PHYS_EXTKBD),
.length = SZ_1M,
.type = MT_DEVICE,
}, { /* CS8900A Ethernet chip */
.virtual = IO_ADDRESS(EP7211_PHYS_CS8900A),
.pfn = __phys_to_pfn(EP7211_PHYS_CS8900A),
.length = SZ_1M,
.type = MT_DEVICE,
}, { /* Flash bank 0 */
.virtual = IO_ADDRESS(EP7211_PHYS_FLASH1),
.pfn = __phys_to_pfn(EP7211_PHYS_FLASH1),
.length = SZ_8M,
.type = MT_DEVICE,
}, { /* Flash bank 1 */
.virtual = IO_ADDRESS(EP7211_PHYS_FLASH2),
.pfn = __phys_to_pfn(EP7211_PHYS_FLASH2),
.length = SZ_8M,
.type = MT_DEVICE,
},
};
void __init edb7211_map_io(void)
{
clps711x_map_io();
iotable_init(edb7211_io_desc, ARRAY_SIZE(edb7211_io_desc));
}
/* Reserve screen memory region at the start of main system memory. */
static void __init edb7211_reserve(void)
{
memblock_reserve(PHYS_OFFSET, 0x00020000);
memblock_reserve(PHYS_OFFSET, VIDEORAM_SIZE);
}
static void __init
@ -48,15 +70,15 @@ fixup_edb7211(struct tag *tags, char **cmdline, struct meminfo *mi)
* not using that information yet.
*/
mi->bank[0].start = 0xc0000000;
mi->bank[0].size = 8*1024*1024;
mi->bank[0].size = SZ_8M;
mi->bank[1].start = 0xc1000000;
mi->bank[1].size = 8*1024*1024;
mi->bank[1].size = SZ_8M;
mi->nr_banks = 2;
}
MACHINE_START(EDB7211, "CL-EDB7211 (EP7211 eval board)")
/* Maintainer: Jon McClintock */
.atag_offset = 0x20100, /* 0xc0000000 - 0xc001ffff can be video RAM */
.atag_offset = VIDEORAM_SIZE + 0x100,
.fixup = fixup_edb7211,
.map_io = edb7211_map_io,
.reserve = edb7211_reserve,

14
arch/arm/mach-clps711x/include/mach/autcpu12.h
View File

@ -20,12 +20,8 @@
#ifndef __ASM_ARCH_AUTCPU12_H
#define __ASM_ARCH_AUTCPU12_H
/*
* The CS8900A ethernet chip has its I/O registers wired to chip select 2
* (nCS2). This is the mapping for it.
*/
#define AUTCPU12_PHYS_CS8900A CS2_PHYS_BASE /* physical */
#define AUTCPU12_VIRT_CS8900A (0xfe000000) /* virtual */
/* The CS8900A ethernet chip has its I/O registers wired to chip select 2 */
#define AUTCPU12_PHYS_CS8900A CS2_PHYS_BASE
/*
* The flash bank is wired to chip select 0
@ -34,11 +30,9 @@
/* offset for device specific information structure */
#define AUTCPU12_LCDINFO_OFFS (0x00010000)
/*
* Videomemory is the internal SRAM (CS 6)
*/
/* Videomemory in the internal SRAM (CS 6) */
#define AUTCPU12_PHYS_VIDEO CS6_PHYS_BASE
#define AUTCPU12_VIRT_VIDEO (0xfd000000)
/*
* All special IO's are tied to CS1

3
arch/arm/mach-clps711x/include/mach/clps711x.h
View File

@ -257,6 +257,9 @@
#define MEMCFG_BUS_WIDTH_16 (0)
#define MEMCFG_BUS_WIDTH_8 (3)
#define MEMCFG_SQAEN (1 << 6)
#define MEMCFG_CLKENB (1 << 7)
#define MEMCFG_WAITSTATE_8_3 (0 << 2)
#define MEMCFG_WAITSTATE_7_3 (1 << 2)
#define MEMCFG_WAITSTATE_6_3 (2 << 2)

56
arch/arm/mach-clps711x/include/mach/hardware.h
View File

@ -24,7 +24,10 @@
#include <mach/clps711x.h>
#define CLPS711X_VIRT_BASE IOMEM(0xff000000)
#define IO_ADDRESS(x) (0xdc000000 + (((x) & 0x03ffffff) | \
(((x) >> 2) & 0x3c000000)))
#define CLPS711X_VIRT_BASE IOMEM(IO_ADDRESS(CLPS711X_PHYS_BASE))
#ifndef __ASSEMBLY__
#define clps_readb(off) readb(CLPS711X_VIRT_BASE + (off))
@ -61,58 +64,25 @@
#define CS7_PHYS_BASE (0x00000000)
#endif
#define SYSPLD_VIRT_BASE 0xfe000000
#define SYSPLD_BASE SYSPLD_VIRT_BASE
#if defined (CONFIG_ARCH_CDB89712)
#define ETHER_START 0x20000000
#define ETHER_SIZE 0x1000
#define ETHER_BASE 0xfe000000
#define ETHER_PHYS_BASE CS2_PHYS_BASE
#define ETHER_SIZE 0x1000
#endif
#if defined (CONFIG_ARCH_EDB7211)
/*
* The extra 8 lines of the keyboard matrix are wired to chip select 3 (nCS3)
* and repeat across it. This is the mapping for it.
*
* In jumpered boot mode, nCS3 is mapped to 0x4000000, not 0x3000000. This
* was cause for much consternation and headscratching. This should probably
* be made a compile/run time kernel option.
*/
#define EP7211_PHYS_EXTKBD CS3_PHYS_BASE /* physical */
/* The extra 8 lines of the keyboard matrix are wired to chip select 3 */
#define EP7211_PHYS_EXTKBD CS3_PHYS_BASE
#define EP7211_VIRT_EXTKBD (0xfd000000) /* virtual */
/* The CS8900A ethernet chip has its I/O registers wired to chip select 2 */
#define EP7211_PHYS_CS8900A CS2_PHYS_BASE
/*
* The CS8900A ethernet chip has its I/O registers wired to chip select 2
* (nCS2). This is the mapping for it.
*
* In jumpered boot mode, nCS2 is mapped to 0x5000000, not 0x2000000. This
* was cause for much consternation and headscratching. This should probably
* be made a compile/run time kernel option.
*/
#define EP7211_PHYS_CS8900A CS2_PHYS_BASE /* physical */
#define EP7211_VIRT_CS8900A (0xfc000000) /* virtual */
/*
* The two flash banks are wired to chip selects 0 and 1. This is the mapping
* for them.
*
* nCS0 and nCS1 are at 0x70000000 and 0x60000000, respectively, when running
* in jumpered boot mode.
*/
#define EP7211_PHYS_FLASH1 CS0_PHYS_BASE /* physical */
#define EP7211_PHYS_FLASH2 CS1_PHYS_BASE /* physical */
#define EP7211_VIRT_FLASH1 (0xfa000000) /* virtual */
#define EP7211_VIRT_FLASH2 (0xfb000000) /* virtual */
/* The two flash banks are wired to chip selects 0 and 1 */
#define EP7211_PHYS_FLASH1 CS0_PHYS_BASE
#define EP7211_PHYS_FLASH2 CS1_PHYS_BASE
#endif /* CONFIG_ARCH_EDB7211 */

4
arch/arm/mach-clps711x/include/mach/irqs.h
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@ -34,8 +34,6 @@
#define IRQ_UMSINT 14
#define IRQ_SSEOTI 15
#define INT1_IRQS (0x0000fff0)
/*
* Interrupts from INTSR2
*/
@ -45,6 +43,4 @@
#define IRQ_UTXINT2 (16+12) /* bit 12 */
#define IRQ_URXINT2 (16+13) /* bit 13 */
#define INT2_IRQS (0x30070000)
#define NR_IRQS 30

9
arch/arm/mach-clps711x/include/mach/syspld.h
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@ -23,14 +23,9 @@
#define __ASM_ARCH_SYSPLD_H
#define SYSPLD_PHYS_BASE (0x10000000)
#define SYSPLD_VIRT_BASE IO_ADDRESS(SYSPLD_PHYS_BASE)
#ifndef __ASSEMBLY__
#include <asm/types.h>
#define SYSPLD_REG(type,off) (*(volatile type *)(SYSPLD_BASE + off))
#else
#define SYSPLD_REG(type,off) (off)
#endif
#define SYSPLD_REG(type, off) (*(volatile type *)(SYSPLD_VIRT_BASE + (off)))
#define PLD_INT SYSPLD_REG(u32, 0x000000)
#define PLD_INT_PENIRQ (1 << 5)

18
arch/arm/mach-clps711x/p720t.c
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@ -36,27 +36,19 @@
#include <asm/mach/map.h>
#include <mach/syspld.h>
#include <asm/hardware/clps7111.h>
#include "common.h"
/*
* Map the P720T system PLD. It occupies two address spaces:
* SYSPLD_PHYS_BASE and SYSPLD_PHYS_BASE + 0x00400000
* We map both here.
* Map the P720T system PLD. It occupies two address spaces:
* 0x10000000 and 0x10400000. We map both regions as one.
*/
static struct map_desc p720t_io_desc[] __initdata = {
{
.virtual = SYSPLD_VIRT_BASE,
.pfn = __phys_to_pfn(SYSPLD_PHYS_BASE),
.length = SZ_1M,
.type = MT_DEVICE
}, {
.virtual = 0xfe400000,
.pfn = __phys_to_pfn(0x10400000),
.length = SZ_1M,
.type = MT_DEVICE
}
.length = SZ_8M,
.type = MT_DEVICE,
},
};
static void __init