ARM: dts: qcom: sdx55: Add QPIC NAND support
Add qpic_nand node to support QPIC NAND controller on SDX55 platform. Since there is no "aon" clock in SDX55, a dummy clock is provided. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20210106125322.61840-11-manivannan.sadhasivam@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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@ -35,6 +35,12 @@
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#clock-cells = <0>;
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#clock-cells = <0>;
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clock-frequency = <32000>;
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clock-frequency = <32000>;
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};
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};
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nand_clk_dummy: nand-clk-dummy {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <32000>;
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};
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};
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};
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cpus {
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cpus {
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@ -149,6 +155,22 @@
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status = "disabled";
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status = "disabled";
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};
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};
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qpic_nand: nand@1b30000 {
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compatible = "qcom,sdx55-nand";
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reg = <0x01b30000 0x10000>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&rpmhcc RPMH_QPIC_CLK>,
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<&nand_clk_dummy>;
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clock-names = "core", "aon";
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dmas = <&qpic_bam 0>,
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<&qpic_bam 1>,
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<&qpic_bam 2>;
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dma-names = "tx", "rx", "cmd";
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status = "disabled";
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};
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tcsr_mutex: hwlock@1f40000 {
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tcsr_mutex: hwlock@1f40000 {
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compatible = "qcom,tcsr-mutex";
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compatible = "qcom,tcsr-mutex";
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reg = <0x01f40000 0x40000>;
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reg = <0x01f40000 0x40000>;
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