ath9k: Use bitops for calibration flags
Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
parent
1e516ca7c9
commit
4b9b42bfe0
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@ -671,7 +671,7 @@ static bool ar9002_hw_calibrate(struct ath_hw *ah,
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nfcal = !!(REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF);
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nfcal = !!(REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF);
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if (ah->caldata)
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if (ah->caldata)
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nfcal_pending = ah->caldata->nfcal_pending;
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nfcal_pending = test_bit(NFCAL_PENDING, &ah->caldata->cal_flags);
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if (currCal && !nfcal &&
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if (currCal && !nfcal &&
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(currCal->calState == CAL_RUNNING ||
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(currCal->calState == CAL_RUNNING ||
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@ -861,7 +861,7 @@ static bool ar9002_hw_init_cal(struct ath_hw *ah, struct ath9k_channel *chan)
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ar9002_hw_pa_cal(ah, true);
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ar9002_hw_pa_cal(ah, true);
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if (ah->caldata)
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if (ah->caldata)
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ah->caldata->nfcal_pending = true;
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set_bit(NFCAL_PENDING, &ah->caldata->cal_flags);
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ah->cal_list = ah->cal_list_last = ah->cal_list_curr = NULL;
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ah->cal_list = ah->cal_list_last = ah->cal_list_curr = NULL;
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@ -727,8 +727,12 @@ static void ar9003_hw_tx_iqcal_load_avg_2_passes(struct ath_hw *ah,
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REG_RMW_FIELD(ah, AR_PHY_RX_IQCAL_CORR_B0,
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REG_RMW_FIELD(ah, AR_PHY_RX_IQCAL_CORR_B0,
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AR_PHY_RX_IQCAL_CORR_B0_LOOPBACK_IQCORR_EN, 0x1);
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AR_PHY_RX_IQCAL_CORR_B0_LOOPBACK_IQCORR_EN, 0x1);
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if (caldata)
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if (caldata) {
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caldata->done_txiqcal_once = is_reusable;
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if (is_reusable)
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set_bit(TXIQCAL_DONE, &caldata->cal_flags);
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else
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clear_bit(TXIQCAL_DONE, &caldata->cal_flags);
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}
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return;
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return;
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}
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}
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@ -990,7 +994,7 @@ static void ar9003_hw_cl_cal_post_proc(struct ath_hw *ah, bool is_reusable)
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txclcal_done = !!(REG_READ(ah, AR_PHY_AGC_CONTROL) &
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txclcal_done = !!(REG_READ(ah, AR_PHY_AGC_CONTROL) &
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AR_PHY_AGC_CONTROL_CLC_SUCCESS);
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AR_PHY_AGC_CONTROL_CLC_SUCCESS);
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if (caldata->done_txclcal_once) {
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if (test_bit(TXCLCAL_DONE, &caldata->cal_flags)) {
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for (i = 0; i < AR9300_MAX_CHAINS; i++) {
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for (i = 0; i < AR9300_MAX_CHAINS; i++) {
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if (!(ah->txchainmask & (1 << i)))
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if (!(ah->txchainmask & (1 << i)))
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continue;
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continue;
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@ -1006,7 +1010,7 @@ static void ar9003_hw_cl_cal_post_proc(struct ath_hw *ah, bool is_reusable)
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caldata->tx_clcal[i][j] =
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caldata->tx_clcal[i][j] =
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REG_READ(ah, CL_TAB_ENTRY(cl_idx[i]));
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REG_READ(ah, CL_TAB_ENTRY(cl_idx[i]));
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}
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}
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caldata->done_txclcal_once = true;
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set_bit(TXCLCAL_DONE, &caldata->cal_flags);
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}
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}
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}
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}
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@ -1053,7 +1057,7 @@ static bool ar9003_hw_init_cal(struct ath_hw *ah,
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}
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}
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if (ah->enabled_cals & TX_CL_CAL) {
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if (ah->enabled_cals & TX_CL_CAL) {
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if (caldata && caldata->done_txclcal_once)
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if (caldata && test_bit(TXCLCAL_DONE, &caldata->cal_flags))
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REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL,
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REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL,
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AR_PHY_CL_CAL_ENABLE);
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AR_PHY_CL_CAL_ENABLE);
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else {
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else {
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@ -1077,14 +1081,14 @@ static bool ar9003_hw_init_cal(struct ath_hw *ah,
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* AGC calibration
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* AGC calibration
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*/
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*/
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if (ah->enabled_cals & TX_IQ_ON_AGC_CAL) {
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if (ah->enabled_cals & TX_IQ_ON_AGC_CAL) {
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if (caldata && !caldata->done_txiqcal_once)
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if (caldata && !test_bit(TXIQCAL_DONE, &caldata->cal_flags))
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REG_SET_BIT(ah, AR_PHY_TX_IQCAL_CONTROL_0,
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REG_SET_BIT(ah, AR_PHY_TX_IQCAL_CONTROL_0,
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AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL);
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AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL);
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else
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else
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REG_CLR_BIT(ah, AR_PHY_TX_IQCAL_CONTROL_0,
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REG_CLR_BIT(ah, AR_PHY_TX_IQCAL_CONTROL_0,
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AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL);
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AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL);
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txiqcal_done = run_agc_cal = true;
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txiqcal_done = run_agc_cal = true;
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} else if (caldata && !caldata->done_txiqcal_once) {
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} else if (caldata && !test_bit(TXIQCAL_DONE, &caldata->cal_flags)) {
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run_agc_cal = true;
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run_agc_cal = true;
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sep_iq_cal = true;
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sep_iq_cal = true;
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}
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}
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@ -1148,7 +1152,7 @@ skip_tx_iqcal:
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if (txiqcal_done)
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if (txiqcal_done)
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ar9003_hw_tx_iq_cal_post_proc(ah, is_reusable);
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ar9003_hw_tx_iq_cal_post_proc(ah, is_reusable);
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else if (caldata && caldata->done_txiqcal_once)
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else if (caldata && test_bit(TXIQCAL_DONE, &caldata->cal_flags))
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ar9003_hw_tx_iq_cal_reload(ah);
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ar9003_hw_tx_iq_cal_reload(ah);
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ar9003_hw_cl_cal_post_proc(ah, is_reusable);
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ar9003_hw_cl_cal_post_proc(ah, is_reusable);
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@ -753,9 +753,9 @@ int ar9003_mci_end_reset(struct ath_hw *ah, struct ath9k_channel *chan,
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1 << AR_PHY_TIMING_CONTROL4_DO_GAIN_DC_IQ_CAL_SHIFT);
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1 << AR_PHY_TIMING_CONTROL4_DO_GAIN_DC_IQ_CAL_SHIFT);
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if (caldata) {
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if (caldata) {
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caldata->done_txiqcal_once = false;
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clear_bit(TXIQCAL_DONE, &caldata->cal_flags);
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caldata->done_txclcal_once = false;
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clear_bit(TXCLCAL_DONE, &caldata->cal_flags);
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caldata->rtt_done = false;
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clear_bit(RTT_DONE, &caldata->cal_flags);
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}
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}
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if (!ath9k_hw_init_cal(ah, chan))
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if (!ath9k_hw_init_cal(ah, chan))
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@ -161,7 +161,7 @@ void ar9003_hw_rtt_fill_hist(struct ath_hw *ah)
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}
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}
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}
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}
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ah->caldata->rtt_done = true;
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set_bit(RTT_DONE, &ah->caldata->cal_flags);
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}
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}
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void ar9003_hw_rtt_clear_hist(struct ath_hw *ah)
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void ar9003_hw_rtt_clear_hist(struct ath_hw *ah)
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@ -176,7 +176,7 @@ void ar9003_hw_rtt_clear_hist(struct ath_hw *ah)
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}
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}
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if (ah->caldata)
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if (ah->caldata)
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ah->caldata->rtt_done = false;
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clear_bit(RTT_DONE, &ah->caldata->cal_flags);
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}
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}
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bool ar9003_hw_rtt_restore(struct ath_hw *ah, struct ath9k_channel *chan)
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bool ar9003_hw_rtt_restore(struct ath_hw *ah, struct ath9k_channel *chan)
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@ -186,7 +186,7 @@ bool ar9003_hw_rtt_restore(struct ath_hw *ah, struct ath9k_channel *chan)
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if (!ah->caldata)
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if (!ah->caldata)
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return false;
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return false;
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if (!ah->caldata->rtt_done)
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if (!test_bit(RTT_DONE, &ah->caldata->cal_flags))
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return false;
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return false;
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ar9003_hw_rtt_enable(ah);
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ar9003_hw_rtt_enable(ah);
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@ -119,7 +119,7 @@ static void ath9k_hw_update_nfcal_hist_buffer(struct ath_hw *ah,
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ath_dbg(common, CALIBRATE,
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ath_dbg(common, CALIBRATE,
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"NFmid[%d] (%d) > MAX (%d), %s\n",
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"NFmid[%d] (%d) > MAX (%d), %s\n",
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i, h[i].privNF, limit->max,
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i, h[i].privNF, limit->max,
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(cal->nfcal_interference ?
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(test_bit(NFCAL_INTF, &cal->cal_flags) ?
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"not corrected (due to interference)" :
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"not corrected (due to interference)" :
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"correcting to MAX"));
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"correcting to MAX"));
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@ -130,7 +130,7 @@ static void ath9k_hw_update_nfcal_hist_buffer(struct ath_hw *ah,
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* we bypass this limit here in order to better deal
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* we bypass this limit here in order to better deal
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* with our environment.
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* with our environment.
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*/
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*/
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if (!cal->nfcal_interference)
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if (!test_bit(NFCAL_INTF, &cal->cal_flags))
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h[i].privNF = limit->max;
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h[i].privNF = limit->max;
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}
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}
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}
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}
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@ -141,7 +141,7 @@ static void ath9k_hw_update_nfcal_hist_buffer(struct ath_hw *ah,
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* Re-enable the enforcement of the NF maximum again.
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* Re-enable the enforcement of the NF maximum again.
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*/
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*/
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if (!high_nf_mid)
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if (!high_nf_mid)
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cal->nfcal_interference = false;
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clear_bit(NFCAL_INTF, &cal->cal_flags);
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}
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}
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static bool ath9k_hw_get_nf_thresh(struct ath_hw *ah,
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static bool ath9k_hw_get_nf_thresh(struct ath_hw *ah,
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@ -220,7 +220,7 @@ EXPORT_SYMBOL(ath9k_hw_reset_calvalid);
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void ath9k_hw_start_nfcal(struct ath_hw *ah, bool update)
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void ath9k_hw_start_nfcal(struct ath_hw *ah, bool update)
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{
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{
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if (ah->caldata)
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if (ah->caldata)
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ah->caldata->nfcal_pending = true;
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set_bit(NFCAL_PENDING, &ah->caldata->cal_flags);
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REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,
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REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,
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AR_PHY_AGC_CONTROL_ENABLE_NF);
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AR_PHY_AGC_CONTROL_ENABLE_NF);
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@ -391,7 +391,7 @@ bool ath9k_hw_getnf(struct ath_hw *ah, struct ath9k_channel *chan)
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}
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}
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h = caldata->nfCalHist;
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h = caldata->nfCalHist;
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caldata->nfcal_pending = false;
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clear_bit(NFCAL_PENDING, &caldata->cal_flags);
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ath9k_hw_update_nfcal_hist_buffer(ah, caldata, nfarray);
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ath9k_hw_update_nfcal_hist_buffer(ah, caldata, nfarray);
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chan->noisefloor = h[0].privNF;
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chan->noisefloor = h[0].privNF;
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ah->noise = ath9k_hw_getchan_noise(ah, chan);
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ah->noise = ath9k_hw_getchan_noise(ah, chan);
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@ -437,12 +437,12 @@ void ath9k_hw_bstuck_nfcal(struct ath_hw *ah)
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* the baseband update the internal NF value itself, similar to
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* the baseband update the internal NF value itself, similar to
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* what is being done after a full reset.
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* what is being done after a full reset.
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*/
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*/
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if (!caldata->nfcal_pending)
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if (!test_bit(NFCAL_PENDING, &caldata->cal_flags))
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ath9k_hw_start_nfcal(ah, true);
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ath9k_hw_start_nfcal(ah, true);
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else if (!(REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF))
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else if (!(REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF))
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ath9k_hw_getnf(ah, ah->curchan);
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ath9k_hw_getnf(ah, ah->curchan);
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caldata->nfcal_interference = true;
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set_bit(NFCAL_INTF, &caldata->cal_flags);
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}
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}
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EXPORT_SYMBOL(ath9k_hw_bstuck_nfcal);
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EXPORT_SYMBOL(ath9k_hw_bstuck_nfcal);
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@ -1847,9 +1847,9 @@ static int ath9k_hw_do_fastcc(struct ath_hw *ah, struct ath9k_channel *chan)
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* re-using are present.
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* re-using are present.
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*/
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*/
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if (AR_SREV_9462(ah) && (ah->caldata &&
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if (AR_SREV_9462(ah) && (ah->caldata &&
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(!ah->caldata->done_txiqcal_once ||
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(!test_bit(TXIQCAL_DONE, &ah->caldata->cal_flags) ||
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!ah->caldata->done_txclcal_once ||
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!test_bit(TXCLCAL_DONE, &ah->caldata->cal_flags) ||
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!ah->caldata->rtt_done)))
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!test_bit(RTT_DONE, &ah->caldata->cal_flags))))
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goto fail;
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goto fail;
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ath_dbg(common, RESET, "FastChannelChange for %d -> %d\n",
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ath_dbg(common, RESET, "FastChannelChange for %d -> %d\n",
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@ -1905,7 +1905,7 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
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memset(caldata, 0, sizeof(*caldata));
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memset(caldata, 0, sizeof(*caldata));
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ath9k_init_nfcal_hist_buffer(ah, chan);
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ath9k_init_nfcal_hist_buffer(ah, chan);
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} else if (caldata) {
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} else if (caldata) {
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caldata->paprd_packet_sent = false;
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clear_bit(PAPRD_PACKET_SENT, &caldata->cal_flags);
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}
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}
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ah->noise = ath9k_hw_getchan_noise(ah, chan);
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ah->noise = ath9k_hw_getchan_noise(ah, chan);
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@ -2042,8 +2042,8 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
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ath9k_hw_init_bb(ah, chan);
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ath9k_hw_init_bb(ah, chan);
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if (caldata) {
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if (caldata) {
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caldata->done_txiqcal_once = false;
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clear_bit(TXIQCAL_DONE, &caldata->cal_flags);
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caldata->done_txclcal_once = false;
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clear_bit(TXCLCAL_DONE, &caldata->cal_flags);
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}
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}
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if (!ath9k_hw_init_cal(ah, chan))
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if (!ath9k_hw_init_cal(ah, chan))
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return -EIO;
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return -EIO;
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@ -404,20 +404,24 @@ enum ath9k_int {
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#define MAX_CL_TAB_ENTRY 16
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#define MAX_CL_TAB_ENTRY 16
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#define CL_TAB_ENTRY(reg_base) (reg_base + (4 * j))
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#define CL_TAB_ENTRY(reg_base) (reg_base + (4 * j))
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enum ath9k_cal_flags {
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RTT_DONE,
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PAPRD_PACKET_SENT,
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PAPRD_DONE,
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NFCAL_PENDING,
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NFCAL_INTF,
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TXIQCAL_DONE,
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TXCLCAL_DONE,
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};
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struct ath9k_hw_cal_data {
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struct ath9k_hw_cal_data {
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u16 channel;
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u16 channel;
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u32 channelFlags;
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u32 channelFlags;
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u32 chanmode;
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u32 chanmode;
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unsigned long cal_flags;
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int32_t CalValid;
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int32_t CalValid;
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int8_t iCoff;
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int8_t iCoff;
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int8_t qCoff;
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int8_t qCoff;
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bool rtt_done;
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bool paprd_packet_sent;
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bool paprd_done;
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bool nfcal_pending;
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bool nfcal_interference;
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bool done_txiqcal_once;
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bool done_txclcal_once;
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u16 small_signal_gain[AR9300_MAX_CHAINS];
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u16 small_signal_gain[AR9300_MAX_CHAINS];
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u32 pa_table[AR9300_MAX_CHAINS][PAPRD_TABLE_SZ];
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u32 pa_table[AR9300_MAX_CHAINS][PAPRD_TABLE_SZ];
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u32 num_measures[AR9300_MAX_CHAINS];
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u32 num_measures[AR9300_MAX_CHAINS];
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@ -184,7 +184,7 @@ static void ath_paprd_activate(struct ath_softc *sc)
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struct ath9k_hw_cal_data *caldata = ah->caldata;
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struct ath9k_hw_cal_data *caldata = ah->caldata;
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int chain;
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int chain;
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if (!caldata || !caldata->paprd_done) {
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if (!caldata || !test_bit(PAPRD_DONE, &caldata->cal_flags)) {
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ath_dbg(common, CALIBRATE, "Failed to activate PAPRD\n");
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ath_dbg(common, CALIBRATE, "Failed to activate PAPRD\n");
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return;
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return;
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}
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}
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@ -256,7 +256,9 @@ void ath_paprd_calibrate(struct work_struct *work)
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int len = 1800;
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int len = 1800;
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int ret;
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int ret;
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if (!caldata || !caldata->paprd_packet_sent || caldata->paprd_done) {
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if (!caldata ||
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!test_bit(PAPRD_PACKET_SENT, &caldata->cal_flags) ||
|
||||||
|
test_bit(PAPRD_DONE, &caldata->cal_flags)) {
|
||||||
ath_dbg(common, CALIBRATE, "Skipping PAPRD calibration\n");
|
ath_dbg(common, CALIBRATE, "Skipping PAPRD calibration\n");
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
|
@ -316,7 +318,7 @@ void ath_paprd_calibrate(struct work_struct *work)
|
||||||
kfree_skb(skb);
|
kfree_skb(skb);
|
||||||
|
|
||||||
if (chain_ok) {
|
if (chain_ok) {
|
||||||
caldata->paprd_done = true;
|
set_bit(PAPRD_DONE, &caldata->cal_flags);
|
||||||
ath_paprd_activate(sc);
|
ath_paprd_activate(sc);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -343,7 +345,7 @@ void ath_ani_calibrate(unsigned long data)
|
||||||
u32 cal_interval, short_cal_interval, long_cal_interval;
|
u32 cal_interval, short_cal_interval, long_cal_interval;
|
||||||
unsigned long flags;
|
unsigned long flags;
|
||||||
|
|
||||||
if (ah->caldata && ah->caldata->nfcal_interference)
|
if (ah->caldata && test_bit(NFCAL_INTF, &ah->caldata->cal_flags))
|
||||||
long_cal_interval = ATH_LONG_CALINTERVAL_INT;
|
long_cal_interval = ATH_LONG_CALINTERVAL_INT;
|
||||||
else
|
else
|
||||||
long_cal_interval = ATH_LONG_CALINTERVAL;
|
long_cal_interval = ATH_LONG_CALINTERVAL;
|
||||||
|
@ -432,7 +434,7 @@ set_timer:
|
||||||
mod_timer(&common->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
|
mod_timer(&common->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
|
||||||
|
|
||||||
if (ar9003_is_paprd_enabled(ah) && ah->caldata) {
|
if (ar9003_is_paprd_enabled(ah) && ah->caldata) {
|
||||||
if (!ah->caldata->paprd_done) {
|
if (!test_bit(PAPRD_DONE, &ah->caldata->cal_flags)) {
|
||||||
ieee80211_queue_work(sc->hw, &sc->paprd_work);
|
ieee80211_queue_work(sc->hw, &sc->paprd_work);
|
||||||
} else if (!ah->paprd_table_write_done) {
|
} else if (!ah->paprd_table_write_done) {
|
||||||
ath9k_ps_wakeup(sc);
|
ath9k_ps_wakeup(sc);
|
||||||
|
|
|
@ -2315,7 +2315,7 @@ static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
|
||||||
ath_dbg(common, XMIT, "TX complete: skb: %p\n", skb);
|
ath_dbg(common, XMIT, "TX complete: skb: %p\n", skb);
|
||||||
|
|
||||||
if (sc->sc_ah->caldata)
|
if (sc->sc_ah->caldata)
|
||||||
sc->sc_ah->caldata->paprd_packet_sent = true;
|
set_bit(PAPRD_PACKET_SENT, &sc->sc_ah->caldata->cal_flags);
|
||||||
|
|
||||||
if (!(tx_flags & ATH_TX_ERROR))
|
if (!(tx_flags & ATH_TX_ERROR))
|
||||||
/* Frame was ACKed */
|
/* Frame was ACKed */
|
||||||
|
|
Loading…
Reference in New Issue