drm/amd/display: make tile changing run at ISR
Signed-off-by: ShihChen Chen <ShihChen.Chen@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -1031,7 +1031,6 @@ static enum surface_update_type get_plane_info_update_type(
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temp_plane_info.plane_size = u->surface->plane_size;
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temp_plane_info.plane_size = u->surface->plane_size;
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temp_plane_info.rotation = u->surface->rotation;
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temp_plane_info.rotation = u->surface->rotation;
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temp_plane_info.stereo_format = u->surface->stereo_format;
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temp_plane_info.stereo_format = u->surface->stereo_format;
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temp_plane_info.tiling_info = u->surface->tiling_info;
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if (surface_index == 0)
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if (surface_index == 0)
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temp_plane_info.visible = u->plane_info->visible;
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temp_plane_info.visible = u->plane_info->visible;
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@ -1044,10 +1043,26 @@ static enum surface_update_type get_plane_info_update_type(
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if (pixel_format_to_bpp(u->plane_info->format) !=
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if (pixel_format_to_bpp(u->plane_info->format) !=
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pixel_format_to_bpp(u->surface->format)) {
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pixel_format_to_bpp(u->surface->format)) {
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/* different bytes per element will require full bandwidth
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* and DML calculation
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*/
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return UPDATE_TYPE_FULL;
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return UPDATE_TYPE_FULL;
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} else {
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return UPDATE_TYPE_MED;
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}
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}
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if (memcmp(&u->plane_info->tiling_info, &u->surface->tiling_info,
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sizeof(union dc_tiling_info)) != 0) {
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/* todo: below are HW dependent, we should add a hook to
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* DCE/N resource and validated there.
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*/
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if (u->plane_info->tiling_info.gfx9.swizzle != DC_SW_LINEAR) {
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/* swizzled mode requires RQ to be setup properly,
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* thus need to run DML to calculate RQ settings
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*/
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return UPDATE_TYPE_FULL;
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}
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}
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return UPDATE_TYPE_MED;
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}
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}
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static enum surface_update_type get_scaling_info_update_type(
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static enum surface_update_type get_scaling_info_update_type(
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