x86/bugs: Remove x86_spec_ctrl_set()
x86_spec_ctrl_set() is only used in bugs.c and the extra mask checks there provide no real value as both call sites can just write x86_spec_ctrl_base to MSR_SPEC_CTRL. x86_spec_ctrl_base is valid and does not need any extra masking or checking. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Borislav Petkov <bp@suse.de> Reviewed-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
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@ -217,8 +217,6 @@ enum spectre_v2_mitigation {
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SPECTRE_V2_IBRS,
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};
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extern void x86_spec_ctrl_set(u64);
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/* The Speculative Store Bypass disable variants */
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enum ssb_mitigation {
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SPEC_STORE_BYPASS_NONE,
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@ -133,15 +133,6 @@ static const char *spectre_v2_strings[] = {
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static enum spectre_v2_mitigation spectre_v2_enabled __ro_after_init =
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SPECTRE_V2_NONE;
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void x86_spec_ctrl_set(u64 val)
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{
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if (val & x86_spec_ctrl_mask)
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WARN_ONCE(1, "SPEC_CTRL MSR value 0x%16llx is unknown.\n", val);
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else
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wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base | val);
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}
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EXPORT_SYMBOL_GPL(x86_spec_ctrl_set);
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void
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x86_virt_spec_ctrl(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl, bool setguest)
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{
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@ -503,7 +494,7 @@ static enum ssb_mitigation __init __ssb_select_mitigation(void)
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case X86_VENDOR_INTEL:
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x86_spec_ctrl_base |= SPEC_CTRL_SSBD;
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x86_spec_ctrl_mask &= ~SPEC_CTRL_SSBD;
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x86_spec_ctrl_set(SPEC_CTRL_SSBD);
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wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
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break;
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case X86_VENDOR_AMD:
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x86_amd_ssb_disable();
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@ -615,7 +606,7 @@ int arch_prctl_spec_ctrl_get(struct task_struct *task, unsigned long which)
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void x86_spec_ctrl_setup_ap(void)
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{
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if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL))
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x86_spec_ctrl_set(x86_spec_ctrl_base & ~x86_spec_ctrl_mask);
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wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
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if (ssb_mode == SPEC_STORE_BYPASS_DISABLE)
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x86_amd_ssb_disable();
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