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r8169: add rtl_enable_exit_l1 

This adds a function for what has been magic register writes so far.
It's based on recent changes to vendor drivers r8101, r8168, r8125,
and deals with events that trigger an early ASPM L1 exit.
Description of the bits has been kindly provided by Realtek.

Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Heiner Kallweit 2021-08-25 18:29:48 +02:00 committed by David S. Miller
parent 9af771d2ec
commit 4b33433ee7
1 changed files with 30 additions and 11 deletions
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41
drivers/net/ethernet/realtek/r8169_main.c
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@ -2669,6 +2669,34 @@ static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp)
RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23);
}
static void rtl_enable_exit_l1(struct rtl8169_private *tp)
{
/* Bits control which events trigger ASPM L1 exit:
* Bit 12: rxdv
* Bit 11: ltr_msg
* Bit 10: txdma_poll
* Bit 9: xadm
* Bit 8: pktavi
* Bit 7: txpla
*/
switch (tp->mac_version) {
case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36:
rtl_eri_set_bits(tp, 0xd4, 0x1f00);
break;
case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_38:
rtl_eri_set_bits(tp, 0xd4, 0x0c00);
break;
case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_53:
rtl_eri_set_bits(tp, 0xd4, 0x1f80);
break;
case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_63:
r8168_mac_ocp_modify(tp, 0xc0ac, 0, 0x1f80);
break;
default:
break;
}
}
static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable)
{
/* Don't enable ASPM in the chip if OS can't control ASPM */
@ -2857,7 +2885,6 @@ static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000);
rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
rtl_eri_set_bits(tp, 0x0d4, 0x1f00);
rtl_eri_set_bits(tp, 0x1d0, BIT(1));
rtl_reset_packet_filter(tp);
rtl_eri_set_bits(tp, 0x1b0, BIT(4));
@ -2914,8 +2941,6 @@ static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
rtl_hw_start_8168f(tp);
rtl_ephy_init(tp, e_info_8168f_1);
rtl_eri_set_bits(tp, 0x0d4, 0x1f00);
}
static void rtl_hw_start_8411(struct rtl8169_private *tp)
@ -2932,8 +2957,6 @@ static void rtl_hw_start_8411(struct rtl8169_private *tp)
rtl_pcie_state_l2l3_disable(tp);
rtl_ephy_init(tp, e_info_8168f_1);
rtl_eri_set_bits(tp, 0x0d4, 0x0c00);
}
static void rtl_hw_start_8168g(struct rtl8169_private *tp)
@ -2950,7 +2973,6 @@ static void rtl_hw_start_8168g(struct rtl8169_private *tp)
rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
rtl_eri_set_bits(tp, 0x0d4, 0x1f80);
rtl8168_config_eee_mac(tp);
@ -3181,7 +3203,6 @@ static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
rtl_reset_packet_filter(tp);
rtl_eri_set_bits(tp, 0xd4, 0x1f00);
rtl_eri_set_bits(tp, 0xdc, 0x001c);
rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
@ -3235,8 +3256,6 @@ static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
rtl_reset_packet_filter(tp);
rtl_eri_set_bits(tp, 0xd4, 0x1f80);
rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
@ -3338,7 +3357,7 @@ static void rtl_hw_start_8117(struct rtl8169_private *tp)
rtl_reset_packet_filter(tp);
rtl_eri_set_bits(tp, 0xd4, 0x1f90);
rtl_eri_set_bits(tp, 0xd4, 0x0010);
rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
@ -3569,7 +3588,6 @@ static void rtl_hw_start_8125_common(struct rtl8169_private *tp)
r8168_mac_ocp_modify(tp, 0xea1c, 0x0003, 0x0001);
r8168_mac_ocp_modify(tp, 0xe0c0, 0x4f0f, 0x4403);
r8168_mac_ocp_modify(tp, 0xe052, 0x0080, 0x0068);
r8168_mac_ocp_modify(tp, 0xc0ac, 0x0080, 0x1f00);
r8168_mac_ocp_modify(tp, 0xd430, 0x0fff, 0x047f);
r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000);
@ -3792,6 +3810,7 @@ static void rtl_hw_start(struct rtl8169_private *tp)
else
rtl_hw_start_8168(tp);
rtl_enable_exit_l1(tp);
rtl_set_rx_max_size(tp);
rtl_set_rx_tx_desc_registers(tp);
rtl_lock_config_regs(tp);