pinctrl: pinctrl-aspeed-g6: Fix register offset for pinconf of GPIOR-T

[ Upstream commit c10cd03d69403fa0f00be8631bd4cb4690440ebd ]

The register offset to disable the internal pull-down of GPIOR~T is 0x630
instead of 0x620, as specified in the Ast2600 datasheet v15
The datasheet can download from the official Aspeed website.

Fixes: 15711ba6ff ("pinctrl: aspeed-g6: Add AST2600 pinconf support")
Reported-by: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>
Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
Reviewed-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-by: Andrew Jeffery <andrew@codeconstruct.com.au>
Message-ID: <20240313092809.2596644-1-billy_tsai@aspeedtech.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Billy Tsai 2024-03-13 17:28:09 +08:00 committed by Greg Kroah-Hartman
parent a381ee26d7
commit 4b1357a277
1 changed files with 17 additions and 17 deletions

View File

@ -43,7 +43,7 @@
#define SCU614 0x614 /* Disable GPIO Internal Pull-Down #1 */ #define SCU614 0x614 /* Disable GPIO Internal Pull-Down #1 */
#define SCU618 0x618 /* Disable GPIO Internal Pull-Down #2 */ #define SCU618 0x618 /* Disable GPIO Internal Pull-Down #2 */
#define SCU61C 0x61c /* Disable GPIO Internal Pull-Down #3 */ #define SCU61C 0x61c /* Disable GPIO Internal Pull-Down #3 */
#define SCU620 0x620 /* Disable GPIO Internal Pull-Down #4 */ #define SCU630 0x630 /* Disable GPIO Internal Pull-Down #4 */
#define SCU634 0x634 /* Disable GPIO Internal Pull-Down #5 */ #define SCU634 0x634 /* Disable GPIO Internal Pull-Down #5 */
#define SCU638 0x638 /* Disable GPIO Internal Pull-Down #6 */ #define SCU638 0x638 /* Disable GPIO Internal Pull-Down #6 */
#define SCU690 0x690 /* Multi-function Pin Control #24 */ #define SCU690 0x690 /* Multi-function Pin Control #24 */
@ -2494,38 +2494,38 @@ static struct aspeed_pin_config aspeed_g6_configs[] = {
ASPEED_PULL_DOWN_PINCONF(D14, SCU61C, 0), ASPEED_PULL_DOWN_PINCONF(D14, SCU61C, 0),
/* GPIOS7 */ /* GPIOS7 */
ASPEED_PULL_DOWN_PINCONF(T24, SCU620, 23), ASPEED_PULL_DOWN_PINCONF(T24, SCU630, 23),
/* GPIOS6 */ /* GPIOS6 */
ASPEED_PULL_DOWN_PINCONF(P23, SCU620, 22), ASPEED_PULL_DOWN_PINCONF(P23, SCU630, 22),
/* GPIOS5 */ /* GPIOS5 */
ASPEED_PULL_DOWN_PINCONF(P24, SCU620, 21), ASPEED_PULL_DOWN_PINCONF(P24, SCU630, 21),
/* GPIOS4 */ /* GPIOS4 */
ASPEED_PULL_DOWN_PINCONF(R26, SCU620, 20), ASPEED_PULL_DOWN_PINCONF(R26, SCU630, 20),
/* GPIOS3*/ /* GPIOS3*/
ASPEED_PULL_DOWN_PINCONF(R24, SCU620, 19), ASPEED_PULL_DOWN_PINCONF(R24, SCU630, 19),
/* GPIOS2 */ /* GPIOS2 */
ASPEED_PULL_DOWN_PINCONF(T26, SCU620, 18), ASPEED_PULL_DOWN_PINCONF(T26, SCU630, 18),
/* GPIOS1 */ /* GPIOS1 */
ASPEED_PULL_DOWN_PINCONF(T25, SCU620, 17), ASPEED_PULL_DOWN_PINCONF(T25, SCU630, 17),
/* GPIOS0 */ /* GPIOS0 */
ASPEED_PULL_DOWN_PINCONF(R23, SCU620, 16), ASPEED_PULL_DOWN_PINCONF(R23, SCU630, 16),
/* GPIOR7 */ /* GPIOR7 */
ASPEED_PULL_DOWN_PINCONF(U26, SCU620, 15), ASPEED_PULL_DOWN_PINCONF(U26, SCU630, 15),
/* GPIOR6 */ /* GPIOR6 */
ASPEED_PULL_DOWN_PINCONF(W26, SCU620, 14), ASPEED_PULL_DOWN_PINCONF(W26, SCU630, 14),
/* GPIOR5 */ /* GPIOR5 */
ASPEED_PULL_DOWN_PINCONF(T23, SCU620, 13), ASPEED_PULL_DOWN_PINCONF(T23, SCU630, 13),
/* GPIOR4 */ /* GPIOR4 */
ASPEED_PULL_DOWN_PINCONF(U25, SCU620, 12), ASPEED_PULL_DOWN_PINCONF(U25, SCU630, 12),
/* GPIOR3*/ /* GPIOR3*/
ASPEED_PULL_DOWN_PINCONF(V26, SCU620, 11), ASPEED_PULL_DOWN_PINCONF(V26, SCU630, 11),
/* GPIOR2 */ /* GPIOR2 */
ASPEED_PULL_DOWN_PINCONF(V24, SCU620, 10), ASPEED_PULL_DOWN_PINCONF(V24, SCU630, 10),
/* GPIOR1 */ /* GPIOR1 */
ASPEED_PULL_DOWN_PINCONF(U24, SCU620, 9), ASPEED_PULL_DOWN_PINCONF(U24, SCU630, 9),
/* GPIOR0 */ /* GPIOR0 */
ASPEED_PULL_DOWN_PINCONF(V25, SCU620, 8), ASPEED_PULL_DOWN_PINCONF(V25, SCU630, 8),
/* GPIOX7 */ /* GPIOX7 */
ASPEED_PULL_DOWN_PINCONF(AB10, SCU634, 31), ASPEED_PULL_DOWN_PINCONF(AB10, SCU634, 31),