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media: venus: hfi: Add 6xx AXI halt logic 

This patch takes the downstream AXI halt routine and applies it when
IS_V6() is true.

bod: Converted to readl_poll_timeout()
     Removed poll timeout for LPI register, testing showed the value
     would always timeout and work, so the polling did nothing of value.

Signed-off-by: Dikshita Agarwal <dikshita@codeaurora.org>
Co-developed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Stanimir Varbanov <stanimir.varbanov@linaro.org>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
This commit is contained in:
Dikshita Agarwal 2021-04-02 12:06:41 +02:00 committed by Mauro Carvalho Chehab
parent c22b1a2949
commit 4b0b6e147d
1 changed files with 32 additions and 0 deletions
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32
drivers/media/platform/qcom/venus/hfi_venus.c
View File

@ -541,10 +541,42 @@ static int venus_halt_axi(struct venus_hfi_device *hdev)
{ {
void __iomem *wrapper_base = hdev->core->wrapper_base; void __iomem *wrapper_base = hdev->core->wrapper_base;
void __iomem *vbif_base = hdev->core->vbif_base; void __iomem *vbif_base = hdev->core->vbif_base;
void __iomem *cpu_cs_base = hdev->core->cpu_cs_base;
void __iomem *aon_base = hdev->core->aon_base;
struct device *dev = hdev->core->dev; struct device *dev = hdev->core->dev;
u32 val; u32 val;
u32 mask_val;
int ret; int ret;
if (IS_V6(hdev->core)) {
writel(0x3, cpu_cs_base + CPU_CS_X2RPMH_V6);
writel(0x1, aon_base + AON_WRAPPER_MVP_NOC_LPI_CONTROL);
ret = readl_poll_timeout(aon_base + AON_WRAPPER_MVP_NOC_LPI_STATUS,
val,
val & BIT(0),
POLL_INTERVAL_US,
VBIF_AXI_HALT_ACK_TIMEOUT_US);
if (ret)
return -ETIMEDOUT;
mask_val = (BIT(2) | BIT(1) | BIT(0));
writel(mask_val, wrapper_base + WRAPPER_DEBUG_BRIDGE_LPI_CONTROL_V6);
writel(0x00, wrapper_base + WRAPPER_DEBUG_BRIDGE_LPI_CONTROL_V6);
ret = readl_poll_timeout(wrapper_base + WRAPPER_DEBUG_BRIDGE_LPI_STATUS_V6,
val,
val == 0,
POLL_INTERVAL_US,
VBIF_AXI_HALT_ACK_TIMEOUT_US);
if (ret) {
dev_err(dev, "DBLP Release: lpi_status %x\n", val);
return -ETIMEDOUT;
}
return 0;
}
if (IS_V4(hdev->core)) { if (IS_V4(hdev->core)) {
val = readl(wrapper_base + WRAPPER_CPU_AXI_HALT); val = readl(wrapper_base + WRAPPER_CPU_AXI_HALT);
val |= WRAPPER_CPU_AXI_HALT_HALT; val |= WRAPPER_CPU_AXI_HALT_HALT;