media: venus: hfi: Add 6xx AXI halt logic
This patch takes the downstream AXI halt routine and applies it when IS_V6() is true. bod: Converted to readl_poll_timeout() Removed poll timeout for LPI register, testing showed the value would always timeout and work, so the polling did nothing of value. Signed-off-by: Dikshita Agarwal <dikshita@codeaurora.org> Co-developed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Stanimir Varbanov <stanimir.varbanov@linaro.org> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
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@ -541,10 +541,42 @@ static int venus_halt_axi(struct venus_hfi_device *hdev)
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{
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void __iomem *wrapper_base = hdev->core->wrapper_base;
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void __iomem *vbif_base = hdev->core->vbif_base;
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void __iomem *cpu_cs_base = hdev->core->cpu_cs_base;
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void __iomem *aon_base = hdev->core->aon_base;
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struct device *dev = hdev->core->dev;
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u32 val;
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u32 mask_val;
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int ret;
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if (IS_V6(hdev->core)) {
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writel(0x3, cpu_cs_base + CPU_CS_X2RPMH_V6);
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writel(0x1, aon_base + AON_WRAPPER_MVP_NOC_LPI_CONTROL);
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ret = readl_poll_timeout(aon_base + AON_WRAPPER_MVP_NOC_LPI_STATUS,
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val,
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val & BIT(0),
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POLL_INTERVAL_US,
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VBIF_AXI_HALT_ACK_TIMEOUT_US);
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if (ret)
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return -ETIMEDOUT;
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mask_val = (BIT(2) | BIT(1) | BIT(0));
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writel(mask_val, wrapper_base + WRAPPER_DEBUG_BRIDGE_LPI_CONTROL_V6);
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writel(0x00, wrapper_base + WRAPPER_DEBUG_BRIDGE_LPI_CONTROL_V6);
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ret = readl_poll_timeout(wrapper_base + WRAPPER_DEBUG_BRIDGE_LPI_STATUS_V6,
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val,
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val == 0,
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POLL_INTERVAL_US,
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VBIF_AXI_HALT_ACK_TIMEOUT_US);
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if (ret) {
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dev_err(dev, "DBLP Release: lpi_status %x\n", val);
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return -ETIMEDOUT;
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}
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return 0;
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}
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if (IS_V4(hdev->core)) {
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val = readl(wrapper_base + WRAPPER_CPU_AXI_HALT);
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val |= WRAPPER_CPU_AXI_HALT_HALT;
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