drm/nouveau/gr/gf100: wait for GR idle after GO_IDLE bundle
After submitting a GO_IDLE bundle, one must wait for GR to effectively be idle before submitting the next bundle. Failure to do so may result in undefined behavior in some rare cases. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Reported-by: Kary Jin <karyj@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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@ -663,6 +663,37 @@ gf100_gr_zbc_init(struct gf100_gr_priv *priv)
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gf100_gr_zbc_clear_depth(priv, index);
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}
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/**
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* Wait until GR goes idle. GR is considered idle if it is disabled by the
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* MC (0x200) register, or GR is not busy and a context switch is not in
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* progress.
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*/
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int
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gf100_gr_wait_idle(struct gf100_gr_priv *priv)
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{
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unsigned long end_jiffies = jiffies + msecs_to_jiffies(2000);
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bool gr_enabled, ctxsw_active, gr_busy;
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do {
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/*
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* required to make sure FIFO_ENGINE_STATUS (0x2640) is
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* up-to-date
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*/
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nv_rd32(priv, 0x400700);
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gr_enabled = nv_rd32(priv, 0x200) & 0x1000;
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ctxsw_active = nv_rd32(priv, 0x2640) & 0x8000;
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gr_busy = nv_rd32(priv, 0x40060c) & 0x1;
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if (!gr_enabled || (!gr_busy && !ctxsw_active))
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return 0;
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} while (time_before(jiffies, end_jiffies));
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nv_error(priv, "wait for idle timeout (en: %d, ctxsw: %d, busy: %d)\n",
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gr_enabled, ctxsw_active, gr_busy);
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return -EAGAIN;
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}
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void
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gf100_gr_mmio(struct gf100_gr_priv *priv, const struct gf100_gr_pack *p)
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{
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@ -699,6 +730,12 @@ gf100_gr_icmd(struct gf100_gr_priv *priv, const struct gf100_gr_pack *p)
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while (addr < next) {
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nv_wr32(priv, 0x400200, addr);
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/**
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* Wait for GR to go idle after submitting a
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* GO_IDLE bundle
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*/
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if ((addr & 0xffff) == 0xe100)
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gf100_gr_wait_idle(priv);
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nv_wait(priv, 0x400700, 0x00000004, 0x00000000);
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addr += init->pitch;
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}
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@ -181,6 +181,7 @@ struct gf100_gr_oclass {
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int ppc_nr;
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};
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int gf100_gr_wait_idle(struct gf100_gr_priv *);
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void gf100_gr_mmio(struct gf100_gr_priv *, const struct gf100_gr_pack *);
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void gf100_gr_icmd(struct gf100_gr_priv *, const struct gf100_gr_pack *);
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void gf100_gr_mthd(struct gf100_gr_priv *, const struct gf100_gr_pack *);
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