drm/amd/display: Fix incorrect dcn1 bandwidth calculations
[WHY] Typos cause bandwidth calculation errors, one of which can cause infinite loop on dcn1 with eDP Signed-off-by: Michael Strauss <michael.strauss@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -805,7 +805,7 @@ void mode_support_and_system_configuration(struct dcn_bw_internal_vars *v)
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if (v->pte_enable == dcn_bw_yes && v->dcc_enable[k] == dcn_bw_yes) {
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v->time_for_meta_pte_without_immediate_flip = dcn_bw_max3(
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v->meta_pte_bytes_frame[k] / v->prefetch_bandwidth[k],
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v->meta_pte_bytes_frame[k] / v->prefetch_bw[k],
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v->extra_latency,
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v->htotal[k] / v->pixel_clock[k] / 4.0);
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} else {
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@ -814,7 +814,7 @@ void mode_support_and_system_configuration(struct dcn_bw_internal_vars *v)
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if (v->pte_enable == dcn_bw_yes || v->dcc_enable[k] == dcn_bw_yes) {
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v->time_for_meta_and_dpte_row_without_immediate_flip = dcn_bw_max3((
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v->meta_row_bytes[k] + v->dpte_bytes_per_row[k]) / v->prefetch_bandwidth[k],
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v->meta_row_bytes[k] + v->dpte_bytes_per_row[k]) / v->prefetch_bw[k],
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v->htotal[k] / v->pixel_clock[k] - v->time_for_meta_pte_without_immediate_flip,
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v->extra_latency);
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} else {
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@ -827,7 +827,7 @@ void mode_support_and_system_configuration(struct dcn_bw_internal_vars *v)
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v->lines_for_meta_and_dpte_row_without_immediate_flip[k] =dcn_bw_floor2(4.0 * (v->time_for_meta_and_dpte_row_without_immediate_flip / (v->htotal[k] / v->pixel_clock[k]) + 0.125), 1.0) / 4;
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v->maximum_vstartup = v->maximum_vstartup - 1;
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if (v->lines_for_meta_pte_without_immediate_flip[k] < 8.0 && v->lines_for_meta_and_dpte_row_without_immediate_flip[k] < 16.0)
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if (v->lines_for_meta_pte_without_immediate_flip[k] < 32.0 && v->lines_for_meta_and_dpte_row_without_immediate_flip[k] < 16.0)
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break;
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} while(1);
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