ARC: [plat-eznps] Add eznps platform
This platform include boards: Hardware Emulator (HE) Simulator based upon nSIM. Signed-off-by: Noam Camus <noamc@ezchip.com>
This commit is contained in:
Noam Camus
Vineet Gupta
parent
845033be00
commit
4a66d3fecf
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@ -4379,6 +4379,12 @@ S: Maintained
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F: drivers/video/fbdev/exynos/exynos_mipi*
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F: drivers/video/fbdev/exynos/exynos_mipi*
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F: include/video/exynos_mipi*
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F: include/video/exynos_mipi*
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EZchip NPS platform support
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M: Noam Camus <noamc@ezchip.com>
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S: Supported
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F: arch/arc/plat-eznps
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F: arch/arc/boot/dts/eznps.dts
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F71805F HARDWARE MONITORING DRIVER
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F71805F HARDWARE MONITORING DRIVER
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M: Jean Delvare <jdelvare@suse.com>
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M: Jean Delvare <jdelvare@suse.com>
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L: linux-hwmon@vger.kernel.org
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L: linux-hwmon@vger.kernel.org
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@ -0,0 +1,35 @@
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#
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# For a description of the syntax of this configuration file,
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# see Documentation/kbuild/kconfig-language.txt.
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#
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menuconfig ARC_PLAT_EZNPS
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bool "\"EZchip\" ARC dev platform"
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select ARC_HAS_COH_CACHES if SMP
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select CPU_BIG_ENDIAN
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select CLKSRC_NPS
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select EZNPS_GIC
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select EZCHIP_NPS_MANAGEMENT_ENET if ETHERNET
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help
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Support for EZchip development platforms,
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based on ARC700 cores.
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We handle few flavours:
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- Hardware Emulator AKA HE which is FPGA based chasis
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- Simulator based on MetaWare nSIM
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- NPS400 chip based on ASIC
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config EZNPS_MTM_EXT
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bool "ARC-EZchip MTM Extensions"
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select CPUMASK_OFFSTACK
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depends on ARC_PLAT_EZNPS && SMP
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default y
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help
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Here we add new hierarchy for CPUs topology.
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We got:
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Core
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Thread
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At the new thread level each CPU represent one HW thread.
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At highest hierarchy each core contain 16 threads,
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any of them seem like CPU from Linux point of view.
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All threads within same core share the execution unit of the
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core and HW scheduler round robin between them.
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@ -0,0 +1,7 @@
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#
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# Makefile for the linux kernel.
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#
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obj-y := entry.o platform.o
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obj-$(CONFIG_SMP) += smp.o
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obj-$(CONFIG_EZNPS_MTM_EXT) += mtm.o
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@ -0,0 +1,70 @@
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/*******************************************************************************
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EZNPS CPU startup Code
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Copyright(c) 2012 EZchip Technologies.
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This program is free software; you can redistribute it and/or modify it
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under the terms and conditions of the GNU General Public License,
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version 2, as published by the Free Software Foundation.
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This program is distributed in the hope it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details.
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The full GNU General Public License is included in this distribution in
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the file called "COPYING".
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*******************************************************************************/
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#include <linux/linkage.h>
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#include <asm/entry.h>
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#include <asm/cache.h>
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#include <plat/ctop.h>
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.cpu A7
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.section .init.text, "ax",@progbits
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.align 1024 ; HW requierment for restart first PC
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ENTRY(res_service)
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#ifdef CONFIG_EZNPS_MTM_EXT
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; There is no work for HW thread id != 0
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lr r3, [CTOP_AUX_THREAD_ID]
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cmp r3, 0
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jne stext
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#endif
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#ifdef CONFIG_ARC_HAS_DCACHE
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; With no cache coherency mechanism D$ need to be used very carefully.
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; Address space:
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; 0G-2G: We disable CONFIG_ARC_CACHE_PAGES.
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; 2G-3G: We disable D$ by setting this bit.
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; 3G-4G: D$ is disabled by architecture.
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; FMT are huge pages for user application reside at 0-2G.
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; Only FMT left as one who can use D$ where each such page got
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; disable/enable bit for cachability.
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; Programmer will use FMT pages for private data so cache coherency
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; would not be a problem.
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; First thing we invalidate D$
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sr 1, [ARC_REG_DC_IVDC]
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sr HW_COMPLY_KRN_NOT_D_CACHED, [CTOP_AUX_HW_COMPLY]
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#endif
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#ifdef CONFIG_SMP
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; We set logical cpuid to be used by GET_CPUID
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; We do not use physical cpuid since we want ids to be continious when
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; it comes to cpus on the same quad cluster.
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; This is useful for applications that used shared resources of a quad
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; cluster such SRAMS.
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lr r3, [CTOP_AUX_CORE_ID]
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sr r3, [CTOP_AUX_LOGIC_CORE_ID]
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lr r3, [CTOP_AUX_CLUSTER_ID]
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; Set logical is acheived by swap of 2 middle bits of cluster id (4 bit)
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; r3 is used since we use short instruction and we need q-class reg
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.short CTOP_INST_MOV2B_FLIP_R3_B1_B2_INST
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.word CTOP_INST_MOV2B_FLIP_R3_B1_B2_LIMM
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sr r3, [CTOP_AUX_LOGIC_CLUSTER_ID]
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#endif
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j stext
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END(res_service)
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@ -0,0 +1,200 @@
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/*
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* Copyright(c) 2015 EZchip Technologies.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* The full GNU General Public License is included in this distribution in
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* the file called "COPYING".
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*/
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#ifndef _PLAT_EZNPS_CTOP_H
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#define _PLAT_EZNPS_CTOP_H
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#ifndef CONFIG_ARC_PLAT_EZNPS
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#error "Incorrect ctop.h include"
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#endif
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#include <soc/nps/common.h>
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/* core auxiliary registers */
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#ifdef __ASSEMBLY__
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#define CTOP_AUX_BASE (-0x800)
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#else
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#define CTOP_AUX_BASE 0xFFFFF800
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#endif
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#define CTOP_AUX_GLOBAL_ID (CTOP_AUX_BASE + 0x000)
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#define CTOP_AUX_CLUSTER_ID (CTOP_AUX_BASE + 0x004)
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#define CTOP_AUX_CORE_ID (CTOP_AUX_BASE + 0x008)
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#define CTOP_AUX_THREAD_ID (CTOP_AUX_BASE + 0x00C)
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#define CTOP_AUX_LOGIC_GLOBAL_ID (CTOP_AUX_BASE + 0x010)
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#define CTOP_AUX_LOGIC_CLUSTER_ID (CTOP_AUX_BASE + 0x014)
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#define CTOP_AUX_LOGIC_CORE_ID (CTOP_AUX_BASE + 0x018)
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#define CTOP_AUX_MT_CTRL (CTOP_AUX_BASE + 0x020)
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#define CTOP_AUX_HW_COMPLY (CTOP_AUX_BASE + 0x024)
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#define CTOP_AUX_LPC (CTOP_AUX_BASE + 0x030)
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#define CTOP_AUX_EFLAGS (CTOP_AUX_BASE + 0x080)
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#define CTOP_AUX_IACK (CTOP_AUX_BASE + 0x088)
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#define CTOP_AUX_GPA1 (CTOP_AUX_BASE + 0x08C)
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#define CTOP_AUX_UDMC (CTOP_AUX_BASE + 0x300)
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/* EZchip core instructions */
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#define CTOP_INST_HWSCHD_OFF_R3 0x3B6F00BF
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#define CTOP_INST_HWSCHD_OFF_R4 0x3C6F00BF
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#define CTOP_INST_HWSCHD_RESTORE_R3 0x3E6F70C3
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#define CTOP_INST_HWSCHD_RESTORE_R4 0x3E6F7103
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#define CTOP_INST_SCHD_RW 0x3E6F7004
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#define CTOP_INST_SCHD_RD 0x3E6F7084
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#define CTOP_INST_ASRI_0_R3 0x3B56003E
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#define CTOP_INST_XEX_DI_R2_R2_R3 0x4A664C00
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#define CTOP_INST_EXC_DI_R2_R2_R3 0x4A664C01
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#define CTOP_INST_AADD_DI_R2_R2_R3 0x4A664C02
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#define CTOP_INST_AAND_DI_R2_R2_R3 0x4A664C04
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#define CTOP_INST_AOR_DI_R2_R2_R3 0x4A664C05
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#define CTOP_INST_AXOR_DI_R2_R2_R3 0x4A664C06
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/* Do not use D$ for address in 2G-3G */
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#define HW_COMPLY_KRN_NOT_D_CACHED _BITUL(28)
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#define NPS_MSU_EN_CFG 0x80
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#define NPS_CRG_BLKID 0x480
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#define NPS_CRG_SYNC_BIT _BITUL(0)
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#define NPS_GIM_BLKID 0x5C0
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/* GIM registers and fields*/
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#define NPS_GIM_UART_LINE _BITUL(7)
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#define NPS_GIM_DBG_LAN_EAST_TX_DONE_LINE _BITUL(10)
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#define NPS_GIM_DBG_LAN_EAST_RX_RDY_LINE _BITUL(11)
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#define NPS_GIM_DBG_LAN_WEST_TX_DONE_LINE _BITUL(25)
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#define NPS_GIM_DBG_LAN_WEST_RX_RDY_LINE _BITUL(26)
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#ifndef __ASSEMBLY__
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/* Functional registers definition */
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struct nps_host_reg_mtm_cfg {
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union {
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struct {
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u32 gen:1, gdis:1, clk_gate_dis:1, asb:1,
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__reserved:9, nat:3, ten:16;
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};
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u32 value;
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};
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};
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struct nps_host_reg_mtm_cpu_cfg {
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union {
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struct {
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u32 csa:22, dmsid:6, __reserved:3, cs:1;
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};
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u32 value;
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};
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};
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struct nps_host_reg_thr_init {
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union {
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struct {
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u32 str:1, __reserved:27, thr_id:4;
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};
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u32 value;
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};
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};
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struct nps_host_reg_thr_init_sts {
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union {
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struct {
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u32 bsy:1, err:1, __reserved:26, thr_id:4;
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};
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u32 value;
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};
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};
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struct nps_host_reg_msu_en_cfg {
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union {
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struct {
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u32 __reserved1:11,
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rtc_en:1, ipc_en:1, gim_1_en:1,
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gim_0_en:1, ipi_en:1, buff_e_rls_bmuw:1,
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buff_e_alc_bmuw:1, buff_i_rls_bmuw:1, buff_i_alc_bmuw:1,
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buff_e_rls_bmue:1, buff_e_alc_bmue:1, buff_i_rls_bmue:1,
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buff_i_alc_bmue:1, __reserved2:1, buff_e_pre_en:1,
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buff_i_pre_en:1, pmuw_ja_en:1, pmue_ja_en:1,
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pmuw_nj_en:1, pmue_nj_en:1, msu_en:1;
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};
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u32 value;
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};
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};
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struct nps_host_reg_gim_p_int_dst {
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union {
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struct {
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u32 int_out_en:1, __reserved1:4,
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is:1, intm:2, __reserved2:4,
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nid:4, __reserved3:4, cid:4,
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__reserved4:4, tid:4;
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};
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u32 value;
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};
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};
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/* AUX registers definition */
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struct nps_host_reg_aux_udmc {
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union {
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struct {
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u32 dcp:1, cme:1, __reserved:19, nat:3,
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__reserved2:5, dcas:3;
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};
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u32 value;
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};
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};
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struct nps_host_reg_aux_mt_ctrl {
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union {
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struct {
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u32 mten:1, hsen:1, scd:1, sten:1,
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st_cnt:8, __reserved:8,
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hs_cnt:8, __reserved1:4;
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};
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u32 value;
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};
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};
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struct nps_host_reg_aux_hw_comply {
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union {
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struct {
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u32 me:1, le:1, te:1, knc:1, __reserved:28;
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};
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u32 value;
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};
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};
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struct nps_host_reg_aux_lpc {
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union {
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struct {
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u32 mep:1, __reserved:31;
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};
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u32 value;
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};
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};
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/* CRG registers */
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#define REG_GEN_PURP_0 nps_host_reg_non_cl(NPS_CRG_BLKID, 0x1BF)
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/* GIM registers */
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#define REG_GIM_P_INT_EN_0 nps_host_reg_non_cl(NPS_GIM_BLKID, 0x100)
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#define REG_GIM_P_INT_POL_0 nps_host_reg_non_cl(NPS_GIM_BLKID, 0x110)
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#define REG_GIM_P_INT_SENS_0 nps_host_reg_non_cl(NPS_GIM_BLKID, 0x114)
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#define REG_GIM_P_INT_BLK_0 nps_host_reg_non_cl(NPS_GIM_BLKID, 0x118)
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#define REG_GIM_P_INT_DST_10 nps_host_reg_non_cl(NPS_GIM_BLKID, 0x13A)
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#define REG_GIM_P_INT_DST_11 nps_host_reg_non_cl(NPS_GIM_BLKID, 0x13B)
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#define REG_GIM_P_INT_DST_25 nps_host_reg_non_cl(NPS_GIM_BLKID, 0x149)
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#define REG_GIM_P_INT_DST_26 nps_host_reg_non_cl(NPS_GIM_BLKID, 0x14A)
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#endif /* __ASSEMBLY__ */
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#endif /* _PLAT_EZNPS_CTOP_H */
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@ -0,0 +1,60 @@
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/*
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* Copyright(c) 2015 EZchip Technologies.
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*
|
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* This program is free software; you can redistribute it and/or modify it
|
||||||
|
* under the terms and conditions of the GNU General Public License,
|
||||||
|
* version 2, as published by the Free Software Foundation.
|
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|
*
|
||||||
|
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||||
|
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||||
|
* more details.
|
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|
*
|
||||||
|
* The full GNU General Public License is included in this distribution in
|
||||||
|
* the file called "COPYING".
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _PLAT_EZNPS_MTM_H
|
||||||
|
#define _PLAT_EZNPS_MTM_H
|
||||||
|
|
||||||
|
#include <plat/ctop.h>
|
||||||
|
|
||||||
|
static inline void *nps_mtm_reg_addr(u32 cpu, u32 reg)
|
||||||
|
{
|
||||||
|
struct global_id gid;
|
||||||
|
u32 core, blkid;
|
||||||
|
|
||||||
|
gid.value = cpu;
|
||||||
|
core = gid.core;
|
||||||
|
blkid = (((core & 0x0C) << 2) | (core & 0x03));
|
||||||
|
|
||||||
|
return nps_host_reg(cpu, blkid, reg);
|
||||||
|
}
|
||||||
|
|
||||||
|
#ifdef CONFIG_EZNPS_MTM_EXT
|
||||||
|
#define NPS_CPU_TO_THREAD_NUM(cpu) \
|
||||||
|
({ struct global_id gid; gid.value = cpu; gid.thread; })
|
||||||
|
|
||||||
|
/* MTM registers */
|
||||||
|
#define MTM_CFG(cpu) nps_mtm_reg_addr(cpu, 0x81)
|
||||||
|
#define MTM_THR_INIT(cpu) nps_mtm_reg_addr(cpu, 0x92)
|
||||||
|
#define MTM_THR_INIT_STS(cpu) nps_mtm_reg_addr(cpu, 0x93)
|
||||||
|
|
||||||
|
#define get_thread(map) map.thread
|
||||||
|
#define eznps_max_cpus 4096
|
||||||
|
#define eznps_cpus_per_cluster 256
|
||||||
|
|
||||||
|
void mtm_enable_core(unsigned int cpu);
|
||||||
|
int mtm_enable_thread(int cpu);
|
||||||
|
#else /* !CONFIG_EZNPS_MTM_EXT */
|
||||||
|
|
||||||
|
#define get_thread(map) 0
|
||||||
|
#define eznps_max_cpus 256
|
||||||
|
#define eznps_cpus_per_cluster 16
|
||||||
|
#define mtm_enable_core(cpu)
|
||||||
|
#define mtm_enable_thread(cpu) 1
|
||||||
|
#define NPS_CPU_TO_THREAD_NUM(cpu) 0
|
||||||
|
|
||||||
|
#endif /* CONFIG_EZNPS_MTM_EXT */
|
||||||
|
|
||||||
|
#endif /* _PLAT_EZNPS_MTM_H */
|
||||||
|
|
@ -0,0 +1,26 @@
|
||||||
|
/*
|
||||||
|
* Copyright(c) 2015 EZchip Technologies.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify it
|
||||||
|
* under the terms and conditions of the GNU General Public License,
|
||||||
|
* version 2, as published by the Free Software Foundation.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||||
|
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||||
|
* more details.
|
||||||
|
*
|
||||||
|
* The full GNU General Public License is included in this distribution in
|
||||||
|
* the file called "COPYING".
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __PLAT_EZNPS_SMP_H
|
||||||
|
#define __PLAT_EZNPS_SMP_H
|
||||||
|
|
||||||
|
#ifdef CONFIG_SMP
|
||||||
|
|
||||||
|
extern void res_service(void);
|
||||||
|
|
||||||
|
#endif /* CONFIG_SMP */
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
@ -0,0 +1,133 @@
|
||||||
|
/*
|
||||||
|
* Copyright(c) 2015 EZchip Technologies.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify it
|
||||||
|
* under the terms and conditions of the GNU General Public License,
|
||||||
|
* version 2, as published by the Free Software Foundation.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||||
|
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||||
|
* more details.
|
||||||
|
*
|
||||||
|
* The full GNU General Public License is included in this distribution in
|
||||||
|
* the file called "COPYING".
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <linux/smp.h>
|
||||||
|
#include <linux/io.h>
|
||||||
|
#include <linux/log2.h>
|
||||||
|
#include <asm/arcregs.h>
|
||||||
|
#include <plat/mtm.h>
|
||||||
|
#include <plat/smp.h>
|
||||||
|
|
||||||
|
#define MT_CTRL_HS_CNT 0xFF
|
||||||
|
#define MT_CTRL_ST_CNT 0xF
|
||||||
|
#define NPS_NUM_HW_THREADS 0x10
|
||||||
|
|
||||||
|
static void mtm_init_nat(int cpu)
|
||||||
|
{
|
||||||
|
struct nps_host_reg_mtm_cfg mtm_cfg;
|
||||||
|
struct nps_host_reg_aux_udmc udmc;
|
||||||
|
int log_nat, nat = 0, i, t;
|
||||||
|
|
||||||
|
/* Iterate core threads and update nat */
|
||||||
|
for (i = 0, t = cpu; i < NPS_NUM_HW_THREADS; i++, t++)
|
||||||
|
nat += test_bit(t, cpumask_bits(cpu_possible_mask));
|
||||||
|
|
||||||
|
log_nat = ilog2(nat);
|
||||||
|
|
||||||
|
udmc.value = read_aux_reg(CTOP_AUX_UDMC);
|
||||||
|
udmc.nat = log_nat;
|
||||||
|
write_aux_reg(CTOP_AUX_UDMC, udmc.value);
|
||||||
|
|
||||||
|
mtm_cfg.value = ioread32be(MTM_CFG(cpu));
|
||||||
|
mtm_cfg.nat = log_nat;
|
||||||
|
iowrite32be(mtm_cfg.value, MTM_CFG(cpu));
|
||||||
|
}
|
||||||
|
|
||||||
|
static void mtm_init_thread(int cpu)
|
||||||
|
{
|
||||||
|
int i, tries = 5;
|
||||||
|
struct nps_host_reg_thr_init thr_init;
|
||||||
|
struct nps_host_reg_thr_init_sts thr_init_sts;
|
||||||
|
|
||||||
|
/* Set thread init register */
|
||||||
|
thr_init.value = 0;
|
||||||
|
iowrite32be(thr_init.value, MTM_THR_INIT(cpu));
|
||||||
|
thr_init.thr_id = NPS_CPU_TO_THREAD_NUM(cpu);
|
||||||
|
thr_init.str = 1;
|
||||||
|
iowrite32be(thr_init.value, MTM_THR_INIT(cpu));
|
||||||
|
|
||||||
|
/* Poll till thread init is done */
|
||||||
|
for (i = 0; i < tries; i++) {
|
||||||
|
thr_init_sts.value = ioread32be(MTM_THR_INIT_STS(cpu));
|
||||||
|
if (thr_init_sts.thr_id == thr_init.thr_id) {
|
||||||
|
if (thr_init_sts.bsy)
|
||||||
|
continue;
|
||||||
|
else if (thr_init_sts.err)
|
||||||
|
pr_warn("Failed to thread init cpu %u\n", cpu);
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
pr_warn("Wrong thread id in thread init for cpu %u\n", cpu);
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (i == tries)
|
||||||
|
pr_warn("Got thread init timeout for cpu %u\n", cpu);
|
||||||
|
}
|
||||||
|
|
||||||
|
int mtm_enable_thread(int cpu)
|
||||||
|
{
|
||||||
|
struct nps_host_reg_mtm_cfg mtm_cfg;
|
||||||
|
|
||||||
|
if (NPS_CPU_TO_THREAD_NUM(cpu) == 0)
|
||||||
|
return 1;
|
||||||
|
|
||||||
|
/* Enable thread in mtm */
|
||||||
|
mtm_cfg.value = ioread32be(MTM_CFG(cpu));
|
||||||
|
mtm_cfg.ten |= (1 << (NPS_CPU_TO_THREAD_NUM(cpu)));
|
||||||
|
iowrite32be(mtm_cfg.value, MTM_CFG(cpu));
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
void mtm_enable_core(unsigned int cpu)
|
||||||
|
{
|
||||||
|
int i;
|
||||||
|
struct nps_host_reg_aux_mt_ctrl mt_ctrl;
|
||||||
|
struct nps_host_reg_mtm_cfg mtm_cfg;
|
||||||
|
|
||||||
|
if (NPS_CPU_TO_THREAD_NUM(cpu) != 0)
|
||||||
|
return;
|
||||||
|
|
||||||
|
/* Initialize Number of Active Threads */
|
||||||
|
mtm_init_nat(cpu);
|
||||||
|
|
||||||
|
/* Initialize mtm_cfg */
|
||||||
|
mtm_cfg.value = ioread32be(MTM_CFG(cpu));
|
||||||
|
mtm_cfg.ten = 1;
|
||||||
|
iowrite32be(mtm_cfg.value, MTM_CFG(cpu));
|
||||||
|
|
||||||
|
/* Initialize all other threads in core */
|
||||||
|
for (i = 1; i < NPS_NUM_HW_THREADS; i++)
|
||||||
|
mtm_init_thread(cpu + i);
|
||||||
|
|
||||||
|
|
||||||
|
/* Enable HW schedule, stall counter, mtm */
|
||||||
|
mt_ctrl.value = 0;
|
||||||
|
mt_ctrl.hsen = 1;
|
||||||
|
mt_ctrl.hs_cnt = MT_CTRL_HS_CNT;
|
||||||
|
mt_ctrl.sten = 1;
|
||||||
|
mt_ctrl.st_cnt = MT_CTRL_ST_CNT;
|
||||||
|
mt_ctrl.mten = 1;
|
||||||
|
write_aux_reg(CTOP_AUX_MT_CTRL, mt_ctrl.value);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* HW scheduling mechanism will start working
|
||||||
|
* Only after call to instruction "schd.rw".
|
||||||
|
* cpu_relax() calls "schd.rw" instruction.
|
||||||
|
*/
|
||||||
|
cpu_relax();
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,102 @@
|
||||||
|
/*
|
||||||
|
* Copyright(c) 2015 EZchip Technologies.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify it
|
||||||
|
* under the terms and conditions of the GNU General Public License,
|
||||||
|
* version 2, as published by the Free Software Foundation.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||||
|
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||||
|
* more details.
|
||||||
|
*
|
||||||
|
* The full GNU General Public License is included in this distribution in
|
||||||
|
* the file called "COPYING".
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <linux/init.h>
|
||||||
|
#include <linux/io.h>
|
||||||
|
#include <asm/mach_desc.h>
|
||||||
|
#include <plat/mtm.h>
|
||||||
|
|
||||||
|
static void __init eznps_configure_msu(void)
|
||||||
|
{
|
||||||
|
int cpu;
|
||||||
|
struct nps_host_reg_msu_en_cfg msu_en_cfg = {.value = 0};
|
||||||
|
|
||||||
|
msu_en_cfg.msu_en = 1;
|
||||||
|
msu_en_cfg.ipi_en = 1;
|
||||||
|
msu_en_cfg.gim_0_en = 1;
|
||||||
|
msu_en_cfg.gim_1_en = 1;
|
||||||
|
|
||||||
|
/* enable IPI and GIM messages on all clusters */
|
||||||
|
for (cpu = 0 ; cpu < eznps_max_cpus; cpu += eznps_cpus_per_cluster)
|
||||||
|
iowrite32be(msu_en_cfg.value,
|
||||||
|
nps_host_reg(cpu, NPS_MSU_BLKID, NPS_MSU_EN_CFG));
|
||||||
|
}
|
||||||
|
|
||||||
|
static void __init eznps_configure_gim(void)
|
||||||
|
{
|
||||||
|
u32 reg_value;
|
||||||
|
u32 gim_int_lines;
|
||||||
|
struct nps_host_reg_gim_p_int_dst gim_p_int_dst = {.value = 0};
|
||||||
|
|
||||||
|
gim_int_lines = NPS_GIM_UART_LINE;
|
||||||
|
gim_int_lines |= NPS_GIM_DBG_LAN_EAST_TX_DONE_LINE;
|
||||||
|
gim_int_lines |= NPS_GIM_DBG_LAN_EAST_RX_RDY_LINE;
|
||||||
|
gim_int_lines |= NPS_GIM_DBG_LAN_WEST_TX_DONE_LINE;
|
||||||
|
gim_int_lines |= NPS_GIM_DBG_LAN_WEST_RX_RDY_LINE;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* IRQ polarity
|
||||||
|
* low or high level
|
||||||
|
* negative or positive edge
|
||||||
|
*/
|
||||||
|
reg_value = ioread32be(REG_GIM_P_INT_POL_0);
|
||||||
|
reg_value &= ~gim_int_lines;
|
||||||
|
iowrite32be(reg_value, REG_GIM_P_INT_POL_0);
|
||||||
|
|
||||||
|
/* IRQ type level or edge */
|
||||||
|
reg_value = ioread32be(REG_GIM_P_INT_SENS_0);
|
||||||
|
reg_value |= NPS_GIM_DBG_LAN_EAST_TX_DONE_LINE;
|
||||||
|
reg_value |= NPS_GIM_DBG_LAN_WEST_TX_DONE_LINE;
|
||||||
|
iowrite32be(reg_value, REG_GIM_P_INT_SENS_0);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* GIM interrupt select type for
|
||||||
|
* dbg_lan TX and RX interrupts
|
||||||
|
* should be type 1
|
||||||
|
* type 0 = IRQ line 6
|
||||||
|
* type 1 = IRQ line 7
|
||||||
|
*/
|
||||||
|
gim_p_int_dst.is = 1;
|
||||||
|
iowrite32be(gim_p_int_dst.value, REG_GIM_P_INT_DST_10);
|
||||||
|
iowrite32be(gim_p_int_dst.value, REG_GIM_P_INT_DST_11);
|
||||||
|
iowrite32be(gim_p_int_dst.value, REG_GIM_P_INT_DST_25);
|
||||||
|
iowrite32be(gim_p_int_dst.value, REG_GIM_P_INT_DST_26);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* CTOP IRQ lines should be defined
|
||||||
|
* as blocking in GIM
|
||||||
|
*/
|
||||||
|
iowrite32be(gim_int_lines, REG_GIM_P_INT_BLK_0);
|
||||||
|
|
||||||
|
/* enable CTOP IRQ lines in GIM */
|
||||||
|
iowrite32be(gim_int_lines, REG_GIM_P_INT_EN_0);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void __init eznps_early_init(void)
|
||||||
|
{
|
||||||
|
eznps_configure_msu();
|
||||||
|
eznps_configure_gim();
|
||||||
|
}
|
||||||
|
|
||||||
|
static const char *eznps_compat[] __initconst = {
|
||||||
|
"ezchip,arc-nps",
|
||||||
|
NULL,
|
||||||
|
};
|
||||||
|
|
||||||
|
MACHINE_START(NPS, "nps")
|
||||||
|
.dt_compat = eznps_compat,
|
||||||
|
.init_early = eznps_early_init,
|
||||||
|
MACHINE_END
|
||||||
|
|
@ -0,0 +1,155 @@
|
||||||
|
/*
|
||||||
|
* Copyright(c) 2015 EZchip Technologies.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify it
|
||||||
|
* under the terms and conditions of the GNU General Public License,
|
||||||
|
* version 2, as published by the Free Software Foundation.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||||
|
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||||
|
* more details.
|
||||||
|
*
|
||||||
|
* The full GNU General Public License is included in this distribution in
|
||||||
|
* the file called "COPYING".
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <linux/smp.h>
|
||||||
|
#include <linux/of_fdt.h>
|
||||||
|
#include <linux/io.h>
|
||||||
|
#include <linux/irqdomain.h>
|
||||||
|
#include <asm/irq.h>
|
||||||
|
#include <plat/ctop.h>
|
||||||
|
#include <plat/smp.h>
|
||||||
|
#include <plat/mtm.h>
|
||||||
|
|
||||||
|
#define NPS_DEFAULT_MSID 0x34
|
||||||
|
#define NPS_MTM_CPU_CFG 0x90
|
||||||
|
|
||||||
|
static char smp_cpuinfo_buf[128] = {"Extn [EZNPS-SMP]\t: On\n"};
|
||||||
|
|
||||||
|
/* Get cpu map from device tree */
|
||||||
|
static int __init eznps_get_map(const char *name, struct cpumask *cpumask)
|
||||||
|
{
|
||||||
|
unsigned long dt_root = of_get_flat_dt_root();
|
||||||
|
const char *buf;
|
||||||
|
|
||||||
|
buf = of_get_flat_dt_prop(dt_root, name, NULL);
|
||||||
|
if (!buf)
|
||||||
|
return 1;
|
||||||
|
|
||||||
|
cpulist_parse(buf, cpumask);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Update board cpu maps */
|
||||||
|
static void __init eznps_init_cpumasks(void)
|
||||||
|
{
|
||||||
|
struct cpumask cpumask;
|
||||||
|
|
||||||
|
if (eznps_get_map("present-cpus", &cpumask)) {
|
||||||
|
pr_err("Failed to get present-cpus from dtb");
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
init_cpu_present(&cpumask);
|
||||||
|
|
||||||
|
if (eznps_get_map("possible-cpus", &cpumask)) {
|
||||||
|
pr_err("Failed to get possible-cpus from dtb");
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
init_cpu_possible(&cpumask);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void eznps_init_core(unsigned int cpu)
|
||||||
|
{
|
||||||
|
u32 sync_value;
|
||||||
|
struct nps_host_reg_aux_hw_comply hw_comply;
|
||||||
|
struct nps_host_reg_aux_lpc lpc;
|
||||||
|
|
||||||
|
if (NPS_CPU_TO_THREAD_NUM(cpu) != 0)
|
||||||
|
return;
|
||||||
|
|
||||||
|
hw_comply.value = read_aux_reg(CTOP_AUX_HW_COMPLY);
|
||||||
|
hw_comply.me = 1;
|
||||||
|
hw_comply.le = 1;
|
||||||
|
hw_comply.te = 1;
|
||||||
|
write_aux_reg(CTOP_AUX_HW_COMPLY, hw_comply.value);
|
||||||
|
|
||||||
|
/* Enable MMU clock */
|
||||||
|
lpc.mep = 1;
|
||||||
|
write_aux_reg(CTOP_AUX_LPC, lpc.value);
|
||||||
|
|
||||||
|
/* Boot CPU only */
|
||||||
|
if (!cpu) {
|
||||||
|
/* Write to general purpose register in CRG */
|
||||||
|
sync_value = ioread32be(REG_GEN_PURP_0);
|
||||||
|
sync_value |= NPS_CRG_SYNC_BIT;
|
||||||
|
iowrite32be(sync_value, REG_GEN_PURP_0);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Master kick starting another CPU
|
||||||
|
*/
|
||||||
|
static void __init eznps_smp_wakeup_cpu(int cpu, unsigned long pc)
|
||||||
|
{
|
||||||
|
struct nps_host_reg_mtm_cpu_cfg cpu_cfg;
|
||||||
|
|
||||||
|
if (mtm_enable_thread(cpu) == 0)
|
||||||
|
return;
|
||||||
|
|
||||||
|
/* set PC, dmsid, and start CPU */
|
||||||
|
cpu_cfg.value = (u32)res_service;
|
||||||
|
cpu_cfg.dmsid = NPS_DEFAULT_MSID;
|
||||||
|
cpu_cfg.cs = 1;
|
||||||
|
iowrite32be(cpu_cfg.value, nps_mtm_reg_addr(cpu, NPS_MTM_CPU_CFG));
|
||||||
|
}
|
||||||
|
|
||||||
|
static void eznps_ipi_send(int cpu)
|
||||||
|
{
|
||||||
|
struct global_id gid;
|
||||||
|
struct {
|
||||||
|
union {
|
||||||
|
struct {
|
||||||
|
u32 num:8, cluster:8, core:8, thread:8;
|
||||||
|
};
|
||||||
|
u32 value;
|
||||||
|
};
|
||||||
|
} ipi;
|
||||||
|
|
||||||
|
gid.value = cpu;
|
||||||
|
ipi.thread = get_thread(gid);
|
||||||
|
ipi.core = gid.core;
|
||||||
|
ipi.cluster = nps_cluster_logic_to_phys(gid.cluster);
|
||||||
|
ipi.num = NPS_IPI_IRQ;
|
||||||
|
|
||||||
|
__asm__ __volatile__(
|
||||||
|
" mov r3, %0\n"
|
||||||
|
" .word %1\n"
|
||||||
|
:
|
||||||
|
: "r"(ipi.value), "i"(CTOP_INST_ASRI_0_R3)
|
||||||
|
: "r3");
|
||||||
|
}
|
||||||
|
|
||||||
|
static void eznps_init_per_cpu(int cpu)
|
||||||
|
{
|
||||||
|
smp_ipi_irq_setup(cpu, NPS_IPI_IRQ);
|
||||||
|
|
||||||
|
eznps_init_core(cpu);
|
||||||
|
mtm_enable_core(cpu);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void eznps_ipi_clear(int irq)
|
||||||
|
{
|
||||||
|
write_aux_reg(CTOP_AUX_IACK, 1 << irq);
|
||||||
|
}
|
||||||
|
|
||||||
|
struct plat_smp_ops plat_smp_ops = {
|
||||||
|
.info = smp_cpuinfo_buf,
|
||||||
|
.init_early_smp = eznps_init_cpumasks,
|
||||||
|
.cpu_kick = eznps_smp_wakeup_cpu,
|
||||||
|
.ipi_send = eznps_ipi_send,
|
||||||
|
.init_per_cpu = eznps_init_per_cpu,
|
||||||
|
.ipi_clear = eznps_ipi_clear,
|
||||||
|
};
|
||||||
Loading…
Reference in New Issue