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Pin control bulk changes for the v6.6 kernel cycle: 

No core changes this time.
 
 Drivers:
 
 - Intel Tangier SoC pin control support.
 
 - AMLogic C3 SoC pin control support.
 
 - Texas Instruments AM654 SoC pin control support.
 
 - Qualcomm SM8350 and SM6115 LPASS (Low Power Audio Sub-System)
   pin control support.
 
 - Qualcomm PMX75 and PM7550BA (Power Management) pin control
   support.
 
 - Qualcomm PMC8180 and PMC8180C (Power Management) pin control
   support.
 
 - DROP the Oxnas driver as there is not enough of community
   interest to keep carrying this ARM(11) port.
 
 Enhancements:
 
 - Bias control in the MT7986 pin control driver.
 
 - Misc device tree binding enhancements such as the Broadcom
   11351 being converted to YAML.
 
 - New macro: DEFINE_NOIRQ_DEV_PM_OPS() put to use.
 
 - Clean up some SPDX headers.
 
 - Handle non-unique devicetree subnode names in two Renesas
   drivers.
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Merge tag 'pinctrl-v6.6-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control updates from Linus Walleij:
 "We have some patches to DTS[I] files in arm and arm64 as well, that
  were merged here as DT headers were being changed.

  The most interesting stuff is the Intel Tangier chip support and
  AMLogic C3 in my opinion.

  No core changes this time.

  Drivers:

   - Intel Tangier SoC pin control support

   - AMLogic C3 SoC pin control support

   - Texas Instruments AM654 SoC pin control support

   - Qualcomm SM8350 and SM6115 LPASS (Low Power Audio Sub-System) pin
     control support

   - Qualcomm PMX75 and PM7550BA (Power Management) pin control support

   - Qualcomm PMC8180 and PMC8180C (Power Management) pin control
     support

   - DROP the Oxnas driver as there is not enough of community interest
     to keep carrying this ARM(11) port

  Enhancements:

   - Bias control in the MT7986 pin control driver

   - Misc device tree binding enhancements such as the Broadcom 11351
     being converted to YAML

   - New macro: DEFINE_NOIRQ_DEV_PM_OPS() put to use

   - Clean up some SPDX headers

   - Handle non-unique devicetree subnode names in two Renesas drivers"

* tag 'pinctrl-v6.6-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (80 commits)
  pinctrl: mlxbf3: Remove gpio_disable_free()
  pinctrl: use capital "OR" for multiple licenses in SPDX
  dt-bindings: pinctrl: renesas,rza2: Use 'additionalProperties' for child nodes
  pinctrl: cherryview: fix address_space_handler() argument
  pinctrl: intel: consolidate ACPI dependency
  pinctrl: tegra: Switch to use DEFINE_NOIRQ_DEV_PM_OPS() helper
  pinctrl: renesas: Switch to use DEFINE_NOIRQ_DEV_PM_OPS() helper
  pinctrl: mvebu: Switch to use DEFINE_NOIRQ_DEV_PM_OPS() helper
  pinctrl: at91: Switch to use DEFINE_NOIRQ_DEV_PM_OPS() helper
  pinctrl: cherryview: Switch to use DEFINE_NOIRQ_DEV_PM_OPS() helper
  pm: Introduce DEFINE_NOIRQ_DEV_PM_OPS() helper
  pinctrl: mediatek: assign functions to configure pin bias on MT7986
  pinctrl: mediatek: fix pull_type data for MT7981
  dt-bindings: pinctrl: aspeed: Allow only defined pin mux node properties
  dt-bindings: pinctrl: Drop 'phandle' properties
  pinctrl: lynxpoint: Make use of pm_ptr()
  pinctrl: baytrail: Make use of pm_ptr()
  pinctrl: intel: Switch to use exported namespace
  pinctrl: lynxpoint: reuse common functions from pinctrl-intel
  pinctrl: cherryview: reuse common functions from pinctrl-intel
  ...
This commit is contained in:
Linus Torvalds 2023-08-30 19:36:19 -07:00
parent bb511d4b25 82a65f0844
commit 4a3b1007ee
228 changed files with 3868 additions and 4297 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
Documentation/devicetree/bindings/arm/omap/ctrl.txt
View File

@ -8,7 +8,7 @@ control module driver itself.
See [2] for documentation about clock/clockdomain nodes. See [2] for documentation about clock/clockdomain nodes.
[1] Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt [1] Documentation/devicetree/bindings/pinctrl/pinctrl-single.yaml
[2] Documentation/devicetree/bindings/clock/ti/* [2] Documentation/devicetree/bindings/clock/ti/*
Required properties: Required properties:

47
Documentation/devicetree/bindings/gpio/gpio_oxnas.txt
View File

@ -1,47 +0,0 @@
* Oxford Semiconductor OXNAS SoC GPIO Controller
Please refer to gpio.txt for generic information regarding GPIO bindings.
Required properties:
- compatible: "oxsemi,ox810se-gpio" or "oxsemi,ox820-gpio"
- reg: Base address and length for the device.
- interrupts: The port interrupt shared by all pins.
- gpio-controller: Marks the port as GPIO controller.
- #gpio-cells: Two. The first cell is the pin number and
the second cell is used to specify the gpio polarity as defined in
defined in <dt-bindings/gpio/gpio.h>:
0 = GPIO_ACTIVE_HIGH
1 = GPIO_ACTIVE_LOW
- interrupt-controller: Marks the device node as an interrupt controller.
- #interrupt-cells: Two. The first cell is the GPIO number and second cell
is used to specify the trigger type as defined in
<dt-bindings/interrupt-controller/irq.h>:
IRQ_TYPE_EDGE_RISING
IRQ_TYPE_EDGE_FALLING
IRQ_TYPE_EDGE_BOTH
- gpio-ranges: Interaction with the PINCTRL subsystem, it also specifies the
gpio base and count, should be in the format of numeric-gpio-range as
specified in the gpio.txt file.
Example:
gpio0: gpio@0 {
compatible = "oxsemi,ox810se-gpio";
reg = <0x000000 0x100000>;
interrupts = <21>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&pinctrl 0 0 32>;
};
keys {
...
button-esc {
label = "ESC";
linux,code = <1>;
gpios = <&gpio0 12 0>;
};
};

5
Documentation/devicetree/bindings/pinctrl/amlogic,meson-pinctrl-a1.yaml
View File

@ -15,6 +15,7 @@ allOf:
properties: properties:
compatible: compatible:
enum: enum:
- amlogic,c3-periphs-pinctrl
- amlogic,meson-a1-periphs-pinctrl - amlogic,meson-a1-periphs-pinctrl
- amlogic,meson-s4-periphs-pinctrl - amlogic,meson-s4-periphs-pinctrl
@ -36,6 +37,10 @@ patternProperties:
- const: mux - const: mux
- const: gpio - const: gpio
gpio-line-names:
minItems: 62 # A1
maxItems: 82 # S4
unevaluatedProperties: unevaluatedProperties:
type: object type: object
$ref: amlogic,meson-pinctrl-common.yaml#/$defs/meson-pins $ref: amlogic,meson-pinctrl-common.yaml#/$defs/meson-pins

7
Documentation/devicetree/bindings/pinctrl/amlogic,meson-pinctrl-common.yaml
View File

@ -41,6 +41,13 @@ $defs:
gpio-ranges: gpio-ranges:
maxItems: 1 maxItems: 1
patternProperties:
"^.+-hog(-[0-9]+)?$":
type: object
required:
- gpio-hog
required: required:
- reg - reg
- reg-names - reg-names

3
Documentation/devicetree/bindings/pinctrl/amlogic,meson-pinctrl-g12a-aobus.yaml
View File

@ -36,6 +36,9 @@ patternProperties:
- const: ds - const: ds
- const: gpio - const: gpio
gpio-line-names:
maxItems: 15
unevaluatedProperties: unevaluatedProperties:
type: object type: object
$ref: amlogic,meson-pinctrl-common.yaml#/$defs/meson-pins $ref: amlogic,meson-pinctrl-common.yaml#/$defs/meson-pins

3
Documentation/devicetree/bindings/pinctrl/amlogic,meson-pinctrl-g12a-periphs.yaml
View File

@ -38,6 +38,9 @@ patternProperties:
- const: mux - const: mux
- const: ds - const: ds
gpio-line-names:
maxItems: 85
unevaluatedProperties: unevaluatedProperties:
type: object type: object
$ref: amlogic,meson-pinctrl-common.yaml#/$defs/meson-pins $ref: amlogic,meson-pinctrl-common.yaml#/$defs/meson-pins

4
Documentation/devicetree/bindings/pinctrl/amlogic,meson8-pinctrl-aobus.yaml
View File

@ -44,6 +44,10 @@ patternProperties:
- const: pull - const: pull
- const: gpio - const: gpio
gpio-line-names:
minItems: 11 # GXL
maxItems: 16 # Meson8
unevaluatedProperties: unevaluatedProperties:
type: object type: object
$ref: amlogic,meson-pinctrl-common.yaml#/$defs/meson-pins $ref: amlogic,meson-pinctrl-common.yaml#/$defs/meson-pins

4
Documentation/devicetree/bindings/pinctrl/amlogic,meson8-pinctrl-cbus.yaml
View File

@ -45,6 +45,10 @@ patternProperties:
- const: pull-enable - const: pull-enable
- const: gpio - const: gpio
gpio-line-names:
minItems: 86 # AXG
maxItems: 120 # Meson8
unevaluatedProperties: unevaluatedProperties:
type: object type: object
$ref: amlogic,meson-pinctrl-common.yaml#/$defs/meson-pins $ref: amlogic,meson-pinctrl-common.yaml#/$defs/meson-pins

52
Documentation/devicetree/bindings/pinctrl/aspeed,ast2400-pinctrl.yaml
View File

@ -25,30 +25,32 @@ properties:
reg: reg:
maxItems: 2 maxItems: 2
patternProperties: additionalProperties:
'^.*$': $ref: pinmux-node.yaml#
if: additionalProperties: false
type: object
then: properties:
patternProperties: pins: true
"^function|groups$": bias-disable: true
$ref: /schemas/types.yaml#/definitions/string
enum: [ ACPI, ADC0, ADC1, ADC10, ADC11, ADC12, ADC13, ADC14, ADC15, patternProperties:
ADC2, ADC3, ADC4, ADC5, ADC6, ADC7, ADC8, ADC9, BMCINT, DDCCLK, DDCDAT, "^function|groups$":
EXTRST, FLACK, FLBUSY, FLWP, GPID, GPID0, GPID2, GPID4, GPID6, GPIE0, enum: [ ACPI, ADC0, ADC1, ADC10, ADC11, ADC12, ADC13, ADC14, ADC15,
GPIE2, GPIE4, GPIE6, I2C10, I2C11, I2C12, I2C13, I2C14, I2C3, I2C4, ADC2, ADC3, ADC4, ADC5, ADC6, ADC7, ADC8, ADC9, BMCINT, DDCCLK, DDCDAT,
I2C5, I2C6, I2C7, I2C8, I2C9, LPCPD, LPCPME, LPCRST, LPCSMI, MAC1LINK, EXTRST, FLACK, FLBUSY, FLWP, GPID, GPID0, GPID2, GPID4, GPID6, GPIE0,
MAC2LINK, MDIO1, MDIO2, NCTS1, NCTS2, NCTS3, NCTS4, NDCD1, NDCD2, GPIE2, GPIE4, GPIE6, I2C10, I2C11, I2C12, I2C13, I2C14, I2C3, I2C4,
NDCD3, NDCD4, NDSR1, NDSR2, NDSR3, NDSR4, NDTR1, NDTR2, NDTR3, NDTR4, I2C5, I2C6, I2C7, I2C8, I2C9, LPCPD, LPCPME, LPCRST, LPCSMI, MAC1LINK,
NDTS4, NRI1, NRI2, NRI3, NRI4, NRTS1, NRTS2, NRTS3, OSCCLK, PWM0, MAC2LINK, MDIO1, MDIO2, NCTS1, NCTS2, NCTS3, NCTS4, NDCD1, NDCD2,
PWM1, PWM2, PWM3, PWM4, PWM5, PWM6, PWM7, RGMII1, RGMII2, RMII1, NDCD3, NDCD4, NDSR1, NDSR2, NDSR3, NDSR4, NDTR1, NDTR2, NDTR3, NDTR4,
RMII2, ROM16, ROM8, ROMCS1, ROMCS2, ROMCS3, ROMCS4, RXD1, RXD2, RXD3, NDTS4, NRI1, NRI2, NRI3, NRI4, NRTS1, NRTS2, NRTS3, OSCCLK, PWM0,
RXD4, SALT1, SALT2, SALT3, SALT4, SD1, SD2, SGPMCK, SGPMI, SGPMLD, PWM1, PWM2, PWM3, PWM4, PWM5, PWM6, PWM7, RGMII1, RGMII2, RMII1,
SGPMO, SGPSCK, SGPSI0, SGPSI1, SGPSLD, SIOONCTRL, SIOPBI, SIOPBO, RMII2, ROM16, ROM8, ROMCS1, ROMCS2, ROMCS3, ROMCS4, RXD1, RXD2, RXD3,
SIOPWREQ, SIOPWRGD, SIOS3, SIOS5, SIOSCI, SPI1, SPI1DEBUG, SPI1PASSTHRU, RXD4, SALT1, SALT2, SALT3, SALT4, SD1, SD2, SGPMCK, SGPMI, SGPMLD,
SPICS1, TIMER3, TIMER4, TIMER5, TIMER6, TIMER7, TIMER8, TXD1, TXD2, SGPMO, SGPSCK, SGPSI0, SGPSI1, SGPSLD, SIOONCTRL, SIOPBI, SIOPBO,
TXD3, TXD4, UART6, USB11D1, USB11H2, USB2D1, USB2H1, USBCKI, VGABIOS_ROM, SIOPWREQ, SIOPWRGD, SIOS3, SIOS5, SIOSCI, SPI1, SPI1DEBUG, SPI1PASSTHRU,
VGAHS, VGAVS, VPI18, VPI24, VPI30, VPO12, VPO24, WDTRST1, WDTRST2] SPICS1, TIMER3, TIMER4, TIMER5, TIMER6, TIMER7, TIMER8, TXD1, TXD2,
TXD3, TXD4, UART6, USB11D1, USB11H2, USB2D1, USB2H1, USBCKI, VGABIOS_ROM,
VGAHS, VGAVS, VPI18, VPI24, VPI30, VPO12, VPO24, WDTRST1, WDTRST2]
allOf: allOf:
- $ref: pinctrl.yaml# - $ref: pinctrl.yaml#
@ -56,8 +58,6 @@ allOf:
required: required:
- compatible - compatible
additionalProperties: false
examples: examples:
- | - |
syscon: scu@1e6e2000 { syscon: scu@1e6e2000 {

56
Documentation/devicetree/bindings/pinctrl/aspeed,ast2500-pinctrl.yaml
View File

@ -37,32 +37,34 @@ properties:
0: compatible with "aspeed,ast2500-gfx", "syscon" 0: compatible with "aspeed,ast2500-gfx", "syscon"
1: compatible with "aspeed,ast2500-lhc", "syscon" 1: compatible with "aspeed,ast2500-lhc", "syscon"
patternProperties: additionalProperties:
'^.*$': $ref: pinmux-node.yaml#
if: additionalProperties: false
type: object
then: properties:
patternProperties: pins: true
"^function|groups$": bias-disable: true
$ref: /schemas/types.yaml#/definitions/string
enum: [ ACPI, ADC0, ADC1, ADC10, ADC11, ADC12, ADC13, ADC14, ADC15, patternProperties:
ADC2, ADC3, ADC4, ADC5, ADC6, ADC7, ADC8, ADC9, BMCINT, DDCCLK, DDCDAT, "^function|groups$":
ESPI, FWSPICS1, FWSPICS2, GPID0, GPID2, GPID4, GPID6, GPIE0, GPIE2, enum: [ ACPI, ADC0, ADC1, ADC10, ADC11, ADC12, ADC13, ADC14, ADC15,
GPIE4, GPIE6, I2C10, I2C11, I2C12, I2C13, I2C14, I2C3, I2C4, I2C5, ADC2, ADC3, ADC4, ADC5, ADC6, ADC7, ADC8, ADC9, BMCINT, DDCCLK, DDCDAT,
I2C6, I2C7, I2C8, I2C9, LAD0, LAD1, LAD2, LAD3, LCLK, LFRAME, LPCHC, ESPI, FWSPICS1, FWSPICS2, GPID0, GPID2, GPID4, GPID6, GPIE0, GPIE2,
LPCPD, LPCPLUS, LPCPME, LPCRST, LPCSMI, LSIRQ, MAC1LINK, MAC2LINK, GPIE4, GPIE6, I2C10, I2C11, I2C12, I2C13, I2C14, I2C3, I2C4, I2C5,
MDIO1, MDIO2, NCTS1, NCTS2, NCTS3, NCTS4, NDCD1, NDCD2, NDCD3, NDCD4, I2C6, I2C7, I2C8, I2C9, LAD0, LAD1, LAD2, LAD3, LCLK, LFRAME, LPCHC,
NDSR1, NDSR2, NDSR3, NDSR4, NDTR1, NDTR2, NDTR3, NDTR4, NRI1, NRI2, LPCPD, LPCPLUS, LPCPME, LPCRST, LPCSMI, LSIRQ, MAC1LINK, MAC2LINK,
NRI3, NRI4, NRTS1, NRTS2, NRTS3, NRTS4, OSCCLK, PEWAKE, PNOR, PWM0, MDIO1, MDIO2, NCTS1, NCTS2, NCTS3, NCTS4, NDCD1, NDCD2, NDCD3, NDCD4,
PWM1, PWM2, PWM3, PWM4, PWM5, PWM6, PWM7, RGMII1, RGMII2, RMII1, NDSR1, NDSR2, NDSR3, NDSR4, NDTR1, NDTR2, NDTR3, NDTR4, NRI1, NRI2,
RMII2, RXD1, RXD2, RXD3, RXD4, SALT1, SALT10, SALT11, SALT12, SALT13, NRI3, NRI4, NRTS1, NRTS2, NRTS3, NRTS4, OSCCLK, PEWAKE, PNOR, PWM0,
SALT14, SALT2, SALT3, SALT4, SALT5, SALT6, SALT7, SALT8, SALT9, SCL1, PWM1, PWM2, PWM3, PWM4, PWM5, PWM6, PWM7, RGMII1, RGMII2, RMII1,
SCL2, SD1, SD2, SDA1, SDA2, SGPS1, SGPS2, SIOONCTRL, SIOPBI, SIOPBO, RMII2, RXD1, RXD2, RXD3, RXD4, SALT1, SALT10, SALT11, SALT12, SALT13,
SIOPWREQ, SIOPWRGD, SIOS3, SIOS5, SIOSCI, SPI1, SPI1CS1, SPI1DEBUG, SALT14, SALT2, SALT3, SALT4, SALT5, SALT6, SALT7, SALT8, SALT9, SCL1,
SPI1PASSTHRU, SPI2CK, SPI2CS0, SPI2CS1, SPI2MISO, SPI2MOSI, TIMER3, SCL2, SD1, SD2, SDA1, SDA2, SGPS1, SGPS2, SIOONCTRL, SIOPBI, SIOPBO,
TIMER4, TIMER5, TIMER6, TIMER7, TIMER8, TXD1, TXD2, TXD3, TXD4, UART6, SIOPWREQ, SIOPWRGD, SIOS3, SIOS5, SIOSCI, SPI1, SPI1CS1, SPI1DEBUG,
USB11BHID, USB2AD, USB2AH, USB2BD, USB2BH, USBCKI, VGABIOSROM, VGAHS, SPI1PASSTHRU, SPI2CK, SPI2CS0, SPI2CS1, SPI2MISO, SPI2MOSI, TIMER3,
VGAVS, VPI24, VPO, WDTRST1, WDTRST2] TIMER4, TIMER5, TIMER6, TIMER7, TIMER8, TXD1, TXD2, TXD3, TXD4, UART6,
USB11BHID, USB2AD, USB2AH, USB2BD, USB2BH, USBCKI, VGABIOSROM, VGAHS,
VGAVS, VPI24, VPO, WDTRST1, WDTRST2]
allOf: allOf:
- $ref: pinctrl.yaml# - $ref: pinctrl.yaml#
@ -71,8 +73,6 @@ required:
- compatible - compatible
- aspeed,external-nodes - aspeed,external-nodes
additionalProperties: false
examples: examples:
- | - |
#include <dt-bindings/clock/aspeed-clock.h> #include <dt-bindings/clock/aspeed-clock.h>

118
Documentation/devicetree/bindings/pinctrl/aspeed,ast2600-pinctrl.yaml
View File

@ -23,65 +23,65 @@ properties:
compatible: compatible:
const: aspeed,ast2600-pinctrl const: aspeed,ast2600-pinctrl
patternProperties: additionalProperties:
'^.*$': $ref: pinmux-node.yaml#
if: additionalProperties: false
type: object
then:
properties:
function:
$ref: /schemas/types.yaml#/definitions/string
enum: [ ADC0, ADC1, ADC10, ADC11, ADC12, ADC13, ADC14, ADC15, ADC2,
ADC3, ADC4, ADC5, ADC6, ADC7, ADC8, ADC9, BMCINT, EMMC, ESPI, ESPIALT,
FSI1, FSI2, FWQSPI, FWSPIABR, FWSPID, FWSPIWP, GPIT0, GPIT1, GPIT2, GPIT3,
GPIT4, GPIT5, GPIT6, GPIT7, GPIU0, GPIU1, GPIU2, GPIU3, GPIU4, GPIU5,
GPIU6, GPIU7, I2C1, I2C10, I2C11, I2C12, I2C13, I2C14, I2C15, I2C16,
I2C2, I2C3, I2C4, I2C5, I2C6, I2C7, I2C8, I2C9, I3C3, I3C4, I3C5,
I3C6, JTAGM, LHPD, LHSIRQ, LPC, LPCHC, LPCPD, LPCPME, LPCSMI, LSIRQ,
MACLINK1, MACLINK2, MACLINK3, MACLINK4, MDIO1, MDIO2, MDIO3, MDIO4,
NCTS1, NCTS2, NCTS3, NCTS4, NDCD1, NDCD2, NDCD3, NDCD4, NDSR1, NDSR2,
NDSR3, NDSR4, NDTR1, NDTR2, NDTR3, NDTR4, NRI1, NRI2, NRI3, NRI4,
NRTS1, NRTS2, NRTS3, NRTS4, OSCCLK, PEWAKE, PWM0, PWM1, PWM10, PWM11,
PWM12, PWM13, PWM14, PWM15, PWM2, PWM3, PWM4, PWM5, PWM6, PWM7, PWM8,
PWM9, RGMII1, RGMII2, RGMII3, RGMII4, RMII1, RMII2, RMII3, RMII4,
RXD1, RXD2, RXD3, RXD4, SALT1, SALT10, SALT11, SALT12, SALT13, SALT14,
SALT15, SALT16, SALT2, SALT3, SALT4, SALT5, SALT6, SALT7, SALT8,
SALT9, SD1, SD2, SGPM1, SGPM2, SGPS1, SGPS2, SIOONCTRL, SIOPBI, SIOPBO,
SIOPWREQ, SIOPWRGD, SIOS3, SIOS5, SIOSCI, SPI1, SPI1ABR, SPI1CS1, SPI1WP, SPI2,
SPI2CS1, SPI2CS2, TACH0, TACH1, TACH10, TACH11, TACH12, TACH13, TACH14,
TACH15, TACH2, TACH3, TACH4, TACH5, TACH6, TACH7, TACH8, TACH9, THRU0,
THRU1, THRU2, THRU3, TXD1, TXD2, TXD3, TXD4, UART10, UART11, UART12,
UART13, UART6, UART7, UART8, UART9, USBAD, USBADP, USB2AH, USB2AHP,
USB2BD, USB2BH, VB, VGAHS, VGAVS, WDTRST1, WDTRST2, WDTRST3, WDTRST4 ]
groups: properties:
$ref: /schemas/types.yaml#/definitions/string function:
enum: [ ADC0, ADC1, ADC10, ADC11, ADC12, ADC13, ADC14, ADC15, ADC2, enum: [ ADC0, ADC1, ADC10, ADC11, ADC12, ADC13, ADC14, ADC15, ADC2,
ADC3, ADC4, ADC5, ADC6, ADC7, ADC8, ADC9, BMCINT, EMMCG1, EMMCG4, ADC3, ADC4, ADC5, ADC6, ADC7, ADC8, ADC9, BMCINT, EMMC, ESPI, ESPIALT,
EMMCG8, ESPI, ESPIALT, FSI1, FSI2, FWQSPI, FWSPIABR, FWSPID, FWSPIWP, FSI1, FSI2, FWQSPI, FWSPIABR, FWSPID, FWSPIWP, GPIT0, GPIT1, GPIT2, GPIT3,
GPIT0, GPIT1, GPIT2, GPIT3, GPIT4, GPIT5, GPIT6, GPIT7, GPIU0, GPIU1, GPIT4, GPIT5, GPIT6, GPIT7, GPIU0, GPIU1, GPIU2, GPIU3, GPIU4, GPIU5,
GPIU2, GPIU3, GPIU4, GPIU5, GPIU6, GPIU7, HVI3C3, HVI3C4, I2C1, I2C10, GPIU6, GPIU7, I2C1, I2C10, I2C11, I2C12, I2C13, I2C14, I2C15, I2C16,
I2C11, I2C12, I2C13, I2C14, I2C15, I2C16, I2C2, I2C3, I2C4, I2C5, I2C2, I2C3, I2C4, I2C5, I2C6, I2C7, I2C8, I2C9, I3C3, I3C4, I3C5,
I2C6, I2C7, I2C8, I2C9, I3C3, I3C4, I3C5, I3C6, JTAGM, LHPD, LHSIRQ, I3C6, JTAGM, LHPD, LHSIRQ, LPC, LPCHC, LPCPD, LPCPME, LPCSMI, LSIRQ,
LPC, LPCHC, LPCPD, LPCPME, LPCSMI, LSIRQ, MACLINK1, MACLINK2, MACLINK3, MACLINK1, MACLINK2, MACLINK3, MACLINK4, MDIO1, MDIO2, MDIO3, MDIO4,
MACLINK4, MDIO1, MDIO2, MDIO3, MDIO4, NCTS1, NCTS2, NCTS3, NCTS4, NCTS1, NCTS2, NCTS3, NCTS4, NDCD1, NDCD2, NDCD3, NDCD4, NDSR1, NDSR2,
NDCD1, NDCD2, NDCD3, NDCD4, NDSR1, NDSR2, NDSR3, NDSR4, NDTR1, NDTR2, NDSR3, NDSR4, NDTR1, NDTR2, NDTR3, NDTR4, NRI1, NRI2, NRI3, NRI4,
NDTR3, NDTR4, NRI1, NRI2, NRI3, NRI4, NRTS1, NRTS2, NRTS3, NRTS4, NRTS1, NRTS2, NRTS3, NRTS4, OSCCLK, PEWAKE, PWM0, PWM1, PWM10, PWM11,
OSCCLK, PEWAKE, PWM0, PWM1, PWM10G0, PWM10G1, PWM11G0, PWM11G1, PWM12G0, PWM12, PWM13, PWM14, PWM15, PWM2, PWM3, PWM4, PWM5, PWM6, PWM7, PWM8,
PWM12G1, PWM13G0, PWM13G1, PWM14G0, PWM14G1, PWM15G0, PWM15G1, PWM2, PWM9, RGMII1, RGMII2, RGMII3, RGMII4, RMII1, RMII2, RMII3, RMII4,
PWM3, PWM4, PWM5, PWM6, PWM7, PWM8G0, PWM8G1, PWM9G0, PWM9G1, QSPI1, RXD1, RXD2, RXD3, RXD4, SALT1, SALT10, SALT11, SALT12, SALT13, SALT14,
QSPI2, RGMII1, RGMII2, RGMII3, RGMII4, RMII1, RMII2, RMII3, RMII4, SALT15, SALT16, SALT2, SALT3, SALT4, SALT5, SALT6, SALT7, SALT8,
RXD1, RXD2, RXD3, RXD4, SALT1, SALT10G0, SALT10G1, SALT11G0, SALT11G1, SALT9, SD1, SD2, SGPM1, SGPM2, SGPS1, SGPS2, SIOONCTRL, SIOPBI, SIOPBO,
SALT12G0, SALT12G1, SALT13G0, SALT13G1, SALT14G0, SALT14G1, SALT15G0, SIOPWREQ, SIOPWRGD, SIOS3, SIOS5, SIOSCI, SPI1, SPI1ABR, SPI1CS1, SPI1WP, SPI2,
SALT15G1, SALT16G0, SALT16G1, SALT2, SALT3, SALT4, SALT5, SALT6, SPI2CS1, SPI2CS2, TACH0, TACH1, TACH10, TACH11, TACH12, TACH13, TACH14,
SALT7, SALT8, SALT9G0, SALT9G1, SD1, SD2, SD3, SGPM1, SGPM2, SGPS1, SGPS2, TACH15, TACH2, TACH3, TACH4, TACH5, TACH6, TACH7, TACH8, TACH9, THRU0,
SIOONCTRL, SIOPBI, SIOPBO, SIOPWREQ, SIOPWRGD, SIOS3, SIOS5, SIOSCI, SPI1, THRU1, THRU2, THRU3, TXD1, TXD2, TXD3, TXD4, UART10, UART11, UART12,
SPI1ABR, SPI1CS1, SPI1WP, SPI2, SPI2CS1, SPI2CS2, TACH0, TACH1, TACH10, TACH11, UART13, UART6, UART7, UART8, UART9, USBAD, USBADP, USB2AH, USB2AHP,
TACH12, TACH13, TACH14, TACH15, TACH2, TACH3, TACH4, TACH5, TACH6, USB2BD, USB2BH, VB, VGAHS, VGAVS, WDTRST1, WDTRST2, WDTRST3, WDTRST4 ]
TACH7, TACH8, TACH9, THRU0, THRU1, THRU2, THRU3, TXD1, TXD2, TXD3,
TXD4, UART10, UART11, UART12G0, UART12G1, UART13G0, UART13G1, UART6, groups:
UART7, UART8, UART9, USBA, USBB, VB, VGAHS, VGAVS, WDTRST1, WDTRST2, enum: [ ADC0, ADC1, ADC10, ADC11, ADC12, ADC13, ADC14, ADC15, ADC2,
WDTRST3, WDTRST4] ADC3, ADC4, ADC5, ADC6, ADC7, ADC8, ADC9, BMCINT, EMMCG1, EMMCG4,
EMMCG8, ESPI, ESPIALT, FSI1, FSI2, FWQSPI, FWSPIABR, FWSPID, FWSPIWP,
GPIT0, GPIT1, GPIT2, GPIT3, GPIT4, GPIT5, GPIT6, GPIT7, GPIU0, GPIU1,
GPIU2, GPIU3, GPIU4, GPIU5, GPIU6, GPIU7, HVI3C3, HVI3C4, I2C1, I2C10,
I2C11, I2C12, I2C13, I2C14, I2C15, I2C16, I2C2, I2C3, I2C4, I2C5,
I2C6, I2C7, I2C8, I2C9, I3C3, I3C4, I3C5, I3C6, JTAGM, LHPD, LHSIRQ,
LPC, LPCHC, LPCPD, LPCPME, LPCSMI, LSIRQ, MACLINK1, MACLINK2, MACLINK3,
MACLINK4, MDIO1, MDIO2, MDIO3, MDIO4, NCTS1, NCTS2, NCTS3, NCTS4,
NDCD1, NDCD2, NDCD3, NDCD4, NDSR1, NDSR2, NDSR3, NDSR4, NDTR1, NDTR2,
NDTR3, NDTR4, NRI1, NRI2, NRI3, NRI4, NRTS1, NRTS2, NRTS3, NRTS4,
OSCCLK, PEWAKE, PWM0, PWM1, PWM10G0, PWM10G1, PWM11G0, PWM11G1, PWM12G0,
PWM12G1, PWM13G0, PWM13G1, PWM14G0, PWM14G1, PWM15G0, PWM15G1, PWM2,
PWM3, PWM4, PWM5, PWM6, PWM7, PWM8G0, PWM8G1, PWM9G0, PWM9G1, QSPI1,
QSPI2, RGMII1, RGMII2, RGMII3, RGMII4, RMII1, RMII2, RMII3, RMII4,
RXD1, RXD2, RXD3, RXD4, SALT1, SALT10G0, SALT10G1, SALT11G0, SALT11G1,
SALT12G0, SALT12G1, SALT13G0, SALT13G1, SALT14G0, SALT14G1, SALT15G0,
SALT15G1, SALT16G0, SALT16G1, SALT2, SALT3, SALT4, SALT5, SALT6,
SALT7, SALT8, SALT9G0, SALT9G1, SD1, SD2, SD3, SGPM1, SGPM2, SGPS1, SGPS2,
SIOONCTRL, SIOPBI, SIOPBO, SIOPWREQ, SIOPWRGD, SIOS3, SIOS5, SIOSCI, SPI1,
SPI1ABR, SPI1CS1, SPI1WP, SPI2, SPI2CS1, SPI2CS2, TACH0, TACH1, TACH10, TACH11,
TACH12, TACH13, TACH14, TACH15, TACH2, TACH3, TACH4, TACH5, TACH6,
TACH7, TACH8, TACH9, THRU0, THRU1, THRU2, THRU3, TXD1, TXD2, TXD3,
TXD4, UART10, UART11, UART12G0, UART12G1, UART13G0, UART13G1, UART6,
UART7, UART8, UART9, USBA, USBB, VB, VGAHS, VGAVS, WDTRST1, WDTRST2,
WDTRST3, WDTRST4]
pins: true
bias-disable: true
allOf: allOf:
- $ref: pinctrl.yaml# - $ref: pinctrl.yaml#
@ -89,8 +89,6 @@ allOf:
required: required:
- compatible - compatible
additionalProperties: false
examples: examples:
- | - |
syscon: scu@1e6e2000 { syscon: scu@1e6e2000 {

461
Documentation/devicetree/bindings/pinctrl/brcm,bcm11351-pinctrl.txt
View File

@ -1,461 +0,0 @@
Broadcom BCM281xx Pin Controller
This is a pin controller for the Broadcom BCM281xx SoC family, which includes
BCM11130, BCM11140, BCM11351, BCM28145, and BCM28155 SoCs.
=== Pin Controller Node ===
Required Properties:
- compatible: Must be "brcm,bcm11351-pinctrl"
- reg: Base address of the PAD Controller register block and the size
of the block.
For example, the following is the bare minimum node:
pinctrl@35004800 {
compatible = "brcm,bcm11351-pinctrl";
reg = <0x35004800 0x430>;
};
As a pin controller device, in addition to the required properties, this node
should also contain the pin configuration nodes that client devices reference,
if any.
=== Pin Configuration Node ===
Each pin configuration node is a sub-node of the pin controller node and is a
container of an arbitrary number of subnodes, called pin group nodes in this
document.
Please refer to the pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the definition of a
"pin configuration node".
=== Pin Group Node ===
A pin group node specifies the desired pin mux and/or pin configuration for an
arbitrary number of pins. The name of the pin group node is optional and not
used.
A pin group node only affects the properties specified in the node, and has no
effect on any properties that are omitted.
The pin group node accepts a subset of the generic pin config properties. For
details generic pin config properties, please refer to pinctrl-bindings.txt
and <include/linux/pinctrl/pinconfig-generic.h>.
Each pin controlled by this pin controller belong to one of three types:
Standard, I2C, and HDMI. Each type accepts a different set of pin config
properties. A list of pins and their types is provided below.
Required Properties (applicable to all pins):
- pins: Multiple strings. Specifies the name(s) of one or more pins to
be configured by this node.
Optional Properties (for standard pins):
- function: String. Specifies the pin mux selection. Values
must be one of: "alt1", "alt2", "alt3", "alt4"
- input-schmitt-enable: No arguments. Enable schmitt-trigger mode.
- input-schmitt-disable: No arguments. Disable schmitt-trigger mode.
- bias-pull-up: No arguments. Pull up on pin.
- bias-pull-down: No arguments. Pull down on pin.
- bias-disable: No arguments. Disable pin bias.
- slew-rate: Integer. Meaning depends on configured pin mux:
*_SCL or *_SDA:
0: Standard(100kbps)& Fast(400kbps) mode
1: Highspeed (3.4Mbps) mode
IC_DM or IC_DP:
0: normal slew rate
1: fast slew rate
Otherwise:
0: fast slew rate
1: normal slew rate
- input-enable: No arguments. Enable input (does not affect
output.)
- input-disable: No arguments. Disable input (does not affect
output.)
- drive-strength: Integer. Drive strength in mA. Valid values are
2, 4, 6, 8, 10, 12, 14, 16 mA.
Optional Properties (for I2C pins):
- function: String. Specifies the pin mux selection. Values
must be one of: "alt1", "alt2", "alt3", "alt4"
- bias-pull-up: Integer. Pull up strength in Ohm. There are 3
pull-up resistors (1.2k, 1.8k, 2.7k) available
in parallel for I2C pins, so the valid values
are: 568, 720, 831, 1080, 1200, 1800, 2700 Ohm.
- bias-disable: No arguments. Disable pin bias.
- slew-rate: Integer. Meaning depends on configured pin mux:
*_SCL or *_SDA:
0: Standard(100kbps)& Fast(400kbps) mode
1: Highspeed (3.4Mbps) mode
IC_DM or IC_DP:
0: normal slew rate
1: fast slew rate
Otherwise:
0: fast slew rate
1: normal slew rate
- input-enable: No arguments. Enable input (does not affect
output.)
- input-disable: No arguments. Disable input (does not affect
output.)
Optional Properties (for HDMI pins):
- function: String. Specifies the pin mux selection. Values
must be one of: "alt1", "alt2", "alt3", "alt4"
- slew-rate: Integer. Controls slew rate.
0: Standard(100kbps)& Fast(400kbps) mode
1: Highspeed (3.4Mbps) mode
- input-enable: No arguments. Enable input (does not affect
output.)
- input-disable: No arguments. Disable input (does not affect
output.)
Example:
// pin controller node
pinctrl@35004800 {
compatible = "brcm,bcm11351-pinctrl";
reg = <0x35004800 0x430>;
// pin configuration node
dev_a_default: dev_a_active {
//group node defining 1 standard pin
grp_1 {
pins = "std_pin1";
function = "alt1";
input-schmitt-enable;
bias-disable;
slew-rate = <1>;
drive-strength = <4>;
};
// group node defining 2 I2C pins
grp_2 {
pins = "i2c_pin1", "i2c_pin2";
function = "alt2";
bias-pull-up = <720>;
input-enable;
};
// group node defining 2 HDMI pins
grp_3 {
pins = "hdmi_pin1", "hdmi_pin2";
function = "alt3";
slew-rate = <1>;
};
// other pin group nodes
...
};
// other pin configuration nodes
...
};
In the example above, "dev_a_active" is a pin configuration node with a number
of sub-nodes. In the pin group node "grp_1", one pin, "std_pin1", is defined in
the "pins" property. Thus, the remaining properties in the "grp_1" node applies
only to this pin, including the following settings:
- setting pinmux to "alt1"
- enabling schmitt-trigger (hystersis) mode
- disabling pin bias
- setting the slew-rate to 1
- setting the drive strength to 4 mA
Note that neither "input-enable" nor "input-disable" was specified - the pinctrl
subsystem will therefore leave this property unchanged from whatever state it
was in before applying these changes.
The "pins" property in the pin group node "grp_2" specifies two pins -
"i2c_pin1" and "i2c_pin2"; the remaining properties in this pin group node,
therefore, applies to both of these pins. The properties include:
- setting pinmux to "alt2"
- setting pull-up resistance to 720 Ohm (ie. enabling 1.2k and 1.8k resistors
in parallel)
- enabling both pins' input
"slew-rate" is not specified in this pin group node, so the slew-rate for these
pins are left as-is.
Finally, "grp_3" defines two HDMI pins. The following properties are applied to
both pins:
- setting pinmux to "alt3"
- setting slew-rate to 1; for HDMI pins, this corresponds to the 3.4 Mbps
Highspeed mode
The input is neither enabled or disabled, and is left untouched.
=== Pin Names and Type ===
The following are valid pin names and their pin types:
"adcsync", Standard
"bat_rm", Standard
"bsc1_scl", I2C
"bsc1_sda", I2C
"bsc2_scl", I2C
"bsc2_sda", I2C
"classgpwr", Standard
"clk_cx8", Standard
"clkout_0", Standard
"clkout_1", Standard
"clkout_2", Standard
"clkout_3", Standard
"clkreq_in_0", Standard
"clkreq_in_1", Standard
"cws_sys_req1", Standard
"cws_sys_req2", Standard
"cws_sys_req3", Standard
"digmic1_clk", Standard
"digmic1_dq", Standard
"digmic2_clk", Standard
"digmic2_dq", Standard
"gpen13", Standard
"gpen14", Standard
"gpen15", Standard
"gpio00", Standard
"gpio01", Standard
"gpio02", Standard
"gpio03", Standard
"gpio04", Standard
"gpio05", Standard
"gpio06", Standard
"gpio07", Standard
"gpio08", Standard
"gpio09", Standard
"gpio10", Standard
"gpio11", Standard
"gpio12", Standard
"gpio13", Standard
"gpio14", Standard
"gps_pablank", Standard
"gps_tmark", Standard
"hdmi_scl", HDMI
"hdmi_sda", HDMI
"ic_dm", Standard
"ic_dp", Standard
"kp_col_ip_0", Standard
"kp_col_ip_1", Standard
"kp_col_ip_2", Standard
"kp_col_ip_3", Standard
"kp_row_op_0", Standard
"kp_row_op_1", Standard
"kp_row_op_2", Standard
"kp_row_op_3", Standard
"lcd_b_0", Standard
"lcd_b_1", Standard
"lcd_b_2", Standard
"lcd_b_3", Standard
"lcd_b_4", Standard
"lcd_b_5", Standard
"lcd_b_6", Standard
"lcd_b_7", Standard
"lcd_g_0", Standard
"lcd_g_1", Standard
"lcd_g_2", Standard
"lcd_g_3", Standard
"lcd_g_4", Standard
"lcd_g_5", Standard
"lcd_g_6", Standard
"lcd_g_7", Standard
"lcd_hsync", Standard
"lcd_oe", Standard
"lcd_pclk", Standard
"lcd_r_0", Standard
"lcd_r_1", Standard
"lcd_r_2", Standard
"lcd_r_3", Standard
"lcd_r_4", Standard
"lcd_r_5", Standard
"lcd_r_6", Standard
"lcd_r_7", Standard
"lcd_vsync", Standard
"mdmgpio0", Standard
"mdmgpio1", Standard
"mdmgpio2", Standard
"mdmgpio3", Standard
"mdmgpio4", Standard
"mdmgpio5", Standard
"mdmgpio6", Standard
"mdmgpio7", Standard
"mdmgpio8", Standard
"mphi_data_0", Standard
"mphi_data_1", Standard
"mphi_data_2", Standard
"mphi_data_3", Standard
"mphi_data_4", Standard
"mphi_data_5", Standard
"mphi_data_6", Standard
"mphi_data_7", Standard
"mphi_data_8", Standard
"mphi_data_9", Standard
"mphi_data_10", Standard
"mphi_data_11", Standard
"mphi_data_12", Standard
"mphi_data_13", Standard
"mphi_data_14", Standard
"mphi_data_15", Standard
"mphi_ha0", Standard
"mphi_hat0", Standard
"mphi_hat1", Standard
"mphi_hce0_n", Standard
"mphi_hce1_n", Standard
"mphi_hrd_n", Standard
"mphi_hwr_n", Standard
"mphi_run0", Standard
"mphi_run1", Standard
"mtx_scan_clk", Standard
"mtx_scan_data", Standard
"nand_ad_0", Standard
"nand_ad_1", Standard
"nand_ad_2", Standard
"nand_ad_3", Standard
"nand_ad_4", Standard
"nand_ad_5", Standard
"nand_ad_6", Standard
"nand_ad_7", Standard
"nand_ale", Standard
"nand_cen_0", Standard
"nand_cen_1", Standard
"nand_cle", Standard
"nand_oen", Standard
"nand_rdy_0", Standard
"nand_rdy_1", Standard
"nand_wen", Standard
"nand_wp", Standard
"pc1", Standard
"pc2", Standard
"pmu_int", Standard
"pmu_scl", I2C
"pmu_sda", I2C
"rfst2g_mtsloten3g", Standard
"rgmii_0_rx_ctl", Standard
"rgmii_0_rxc", Standard
"rgmii_0_rxd_0", Standard
"rgmii_0_rxd_1", Standard
"rgmii_0_rxd_2", Standard
"rgmii_0_rxd_3", Standard
"rgmii_0_tx_ctl", Standard
"rgmii_0_txc", Standard
"rgmii_0_txd_0", Standard
"rgmii_0_txd_1", Standard
"rgmii_0_txd_2", Standard
"rgmii_0_txd_3", Standard
"rgmii_1_rx_ctl", Standard
"rgmii_1_rxc", Standard
"rgmii_1_rxd_0", Standard
"rgmii_1_rxd_1", Standard
"rgmii_1_rxd_2", Standard
"rgmii_1_rxd_3", Standard
"rgmii_1_tx_ctl", Standard
"rgmii_1_txc", Standard
"rgmii_1_txd_0", Standard
"rgmii_1_txd_1", Standard
"rgmii_1_txd_2", Standard
"rgmii_1_txd_3", Standard
"rgmii_gpio_0", Standard
"rgmii_gpio_1", Standard
"rgmii_gpio_2", Standard
"rgmii_gpio_3", Standard
"rtxdata2g_txdata3g1", Standard
"rtxen2g_txdata3g2", Standard
"rxdata3g0", Standard
"rxdata3g1", Standard
"rxdata3g2", Standard
"sdio1_clk", Standard
"sdio1_cmd", Standard
"sdio1_data_0", Standard
"sdio1_data_1", Standard
"sdio1_data_2", Standard
"sdio1_data_3", Standard
"sdio4_clk", Standard
"sdio4_cmd", Standard
"sdio4_data_0", Standard
"sdio4_data_1", Standard
"sdio4_data_2", Standard
"sdio4_data_3", Standard
"sim_clk", Standard
"sim_data", Standard
"sim_det", Standard
"sim_resetn", Standard
"sim2_clk", Standard
"sim2_data", Standard
"sim2_det", Standard
"sim2_resetn", Standard
"sri_c", Standard
"sri_d", Standard
"sri_e", Standard
"ssp_extclk", Standard
"ssp0_clk", Standard
"ssp0_fs", Standard
"ssp0_rxd", Standard
"ssp0_txd", Standard
"ssp2_clk", Standard
"ssp2_fs_0", Standard
"ssp2_fs_1", Standard
"ssp2_fs_2", Standard
"ssp2_fs_3", Standard
"ssp2_rxd_0", Standard
"ssp2_rxd_1", Standard
"ssp2_txd_0", Standard
"ssp2_txd_1", Standard
"ssp3_clk", Standard
"ssp3_fs", Standard
"ssp3_rxd", Standard
"ssp3_txd", Standard
"ssp4_clk", Standard
"ssp4_fs", Standard
"ssp4_rxd", Standard
"ssp4_txd", Standard
"ssp5_clk", Standard
"ssp5_fs", Standard
"ssp5_rxd", Standard
"ssp5_txd", Standard
"ssp6_clk", Standard
"ssp6_fs", Standard
"ssp6_rxd", Standard
"ssp6_txd", Standard
"stat_1", Standard
"stat_2", Standard
"sysclken", Standard
"traceclk", Standard
"tracedt00", Standard
"tracedt01", Standard
"tracedt02", Standard
"tracedt03", Standard
"tracedt04", Standard
"tracedt05", Standard
"tracedt06", Standard
"tracedt07", Standard
"tracedt08", Standard
"tracedt09", Standard
"tracedt10", Standard
"tracedt11", Standard
"tracedt12", Standard
"tracedt13", Standard
"tracedt14", Standard
"tracedt15", Standard
"txdata3g0", Standard
"txpwrind", Standard
"uartb1_ucts", Standard
"uartb1_urts", Standard
"uartb1_urxd", Standard
"uartb1_utxd", Standard
"uartb2_urxd", Standard
"uartb2_utxd", Standard
"uartb3_ucts", Standard
"uartb3_urts", Standard
"uartb3_urxd", Standard
"uartb3_utxd", Standard
"uartb4_ucts", Standard
"uartb4_urts", Standard
"uartb4_urxd", Standard
"uartb4_utxd", Standard
"vc_cam1_scl", I2C
"vc_cam1_sda", I2C
"vc_cam2_scl", I2C
"vc_cam2_sda", I2C
"vc_cam3_scl", I2C
"vc_cam3_sda", I2C

259
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@ -0,0 +1,259 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/brcm,bcm11351-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom BCM281xx pin controller
maintainers:
- Florian Fainelli <florian.fainelli@broadcom.com>
- Ray Jui <rjui@broadcom.com>
- Scott Branden <sbranden@broadcom.com>
allOf:
- $ref: pinctrl.yaml#
properties:
compatible:
const: brcm,bcm11351-pinctrl
reg:
maxItems: 1
patternProperties:
'-pins$':
type: object
additionalProperties: false
patternProperties:
'-grp[0-9]$':
type: object
unevaluatedProperties: false
properties:
pins:
description:
Specifies the name(s) of one or more pins to be configured by
this node.
items:
enum: [ adcsync, bat_rm, bsc1_scl, bsc1_sda, bsc2_scl, bsc2_sda,
classgpwr, clk_cx8, clkout_0, clkout_1, clkout_2,
clkout_3, clkreq_in_0, clkreq_in_1, cws_sys_req1,
cws_sys_req2, cws_sys_req3, digmic1_clk, digmic1_dq,
digmic2_clk, digmic2_dq, gpen13, gpen14, gpen15, gpio00,
gpio01, gpio02, gpio03, gpio04, gpio05, gpio06, gpio07,
gpio08, gpio09, gpio10, gpio11, gpio12, gpio13, gpio14,
gps_pablank, gps_tmark, hdmi_scl, hdmi_sda, ic_dm, ic_dp,
kp_col_ip_0, kp_col_ip_1, kp_col_ip_2, kp_col_ip_3,
kp_row_op_0, kp_row_op_1, kp_row_op_2, kp_row_op_3,
lcd_b_0, lcd_b_1, lcd_b_2, lcd_b_3, lcd_b_4, lcd_b_5,
lcd_b_6, lcd_b_7, lcd_g_0, lcd_g_1, lcd_g_2, lcd_g_3,
lcd_g_4, lcd_g_5, lcd_g_6, lcd_g_7, lcd_hsync, lcd_oe,
lcd_pclk, lcd_r_0, lcd_r_1, lcd_r_2, lcd_r_3, lcd_r_4,
lcd_r_5, lcd_r_6, lcd_r_7, lcd_vsync, mdmgpio0, mdmgpio1,
mdmgpio2, mdmgpio3, mdmgpio4, mdmgpio5, mdmgpio6,
mdmgpio7, mdmgpio8, mphi_data_0, mphi_data_1, mphi_data_2,
mphi_data_3, mphi_data_4, mphi_data_5, mphi_data_6,
mphi_data_7, mphi_data_8, mphi_data_9, mphi_data_10,
mphi_data_11, mphi_data_12, mphi_data_13, mphi_data_14,
mphi_data_15, mphi_ha0, mphi_hat0, mphi_hat1, mphi_hce0_n,
mphi_hce1_n, mphi_hrd_n, mphi_hwr_n, mphi_run0, mphi_run1,
mtx_scan_clk, mtx_scan_data, nand_ad_0, nand_ad_1,
nand_ad_2, nand_ad_3, nand_ad_4, nand_ad_5, nand_ad_6,
nand_ad_7, nand_ale, nand_cen_0, nand_cen_1, nand_cle,
nand_oen, nand_rdy_0, nand_rdy_1, nand_wen, nand_wp, pc1,
pc2, pmu_int, pmu_scl, pmu_sda, rfst2g_mtsloten3g,
rgmii_0_rx_ctl, rgmii_0_rxc, rgmii_0_rxd_0, rgmii_0_rxd_1,
rgmii_0_rxd_2, rgmii_0_rxd_3, rgmii_0_tx_ctl, rgmii_0_txc,
rgmii_0_txd_0, rgmii_0_txd_1, rgmii_0_txd_2,
rgmii_0_txd_3, rgmii_1_rx_ctl, rgmii_1_rxc, rgmii_1_rxd_0,
rgmii_1_rxd_1, rgmii_1_rxd_2, rgmii_1_rxd_3,
rgmii_1_tx_ctl, rgmii_1_txc, rgmii_1_txd_0, rgmii_1_txd_1,
rgmii_1_txd_2, rgmii_1_txd_3, rgmii_gpio_0, rgmii_gpio_1,
rgmii_gpio_2, rgmii_gpio_3, rtxdata2g_txdata3g1,
rtxen2g_txdata3g2, rxdata3g0, rxdata3g1, rxdata3g2,
sdio1_clk, sdio1_cmd, sdio1_data_0, sdio1_data_1,
sdio1_data_2, sdio1_data_3, sdio4_clk, sdio4_cmd,
sdio4_data_0, sdio4_data_1, sdio4_data_2, sdio4_data_3,
sim_clk, sim_data, sim_det, sim_resetn, sim2_clk,
sim2_data, sim2_det, sim2_resetn, sri_c, sri_d, sri_e,
ssp_extclk, ssp0_clk, ssp0_fs, ssp0_rxd, ssp0_txd,
ssp2_clk, ssp2_fs_0, ssp2_fs_1, ssp2_fs_2, ssp2_fs_3,
ssp2_rxd_0, ssp2_rxd_1, ssp2_txd_0, ssp2_txd_1, ssp3_clk,
ssp3_fs, ssp3_rxd, ssp3_txd, ssp4_clk, ssp4_fs, ssp4_rxd,
ssp4_txd, ssp5_clk, ssp5_fs, ssp5_rxd, ssp5_txd, ssp6_clk,
ssp6_fs, ssp6_rxd, ssp6_txd, stat_1, stat_2, sysclken,
traceclk, tracedt00, tracedt01, tracedt02, tracedt03,
tracedt04, tracedt05, tracedt06, tracedt07, tracedt08
tracedt09, tracedt10, tracedt11, tracedt12, tracedt13
tracedt14, tracedt15, txdata3g0, txpwrind, uartb1_ucts,
uartb1_urts, uartb1_urxd, uartb1_utxd, uartb2_urxd,
uartb2_utxd, uartb3_ucts, uartb3_urts, uartb3_urxd,
uartb3_utxd, uartb4_ucts, uartb4_urts, uartb4_urxd,
uartb4_utxd, vc_cam1_scl, vc_cam1_sda, vc_cam2_scl,
vc_cam2_sda, vc_cam3_scl, vc_cam3_sda ]
function:
description:
Specifies the pin mux selection.
enum: [ alt1, alt2, alt3, alt4 ]
slew-rate:
description: |
Meaning depends on configured pin mux:
*_scl or *_sda:
0: Standard (100 kbps) & Fast (400 kbps) mode
1: Highspeed (3.4 Mbps) mode
ic_dm or ic_dp:
0: normal slew rate
1: fast slew rate
Otherwise:
0: fast slew rate
1: normal slew rate
bias-disable: true
input-disable: true
input-enable: true
required:
- pins
allOf:
- $ref: pincfg-node.yaml#
# Optional properties for standard pins
- if:
properties:
pins:
contains:
enum: [ adcsync, bat_rm, classgpwr, clk_cx8, clkout_0,
clkout_1, clkout_2, clkout_3, clkreq_in_0,
clkreq_in_1, cws_sys_req1, cws_sys_req2,
cws_sys_req3, digmic1_clk, digmic1_dq, digmic2_clk,
digmic2_dq, gpen13, gpen14, gpen15, gpio00, gpio01,
gpio02, gpio03, gpio04, gpio05, gpio06, gpio07,
gpio08, gpio09, gpio10, gpio11, gpio12, gpio13,
gpio14, gps_pablank, gps_tmark, ic_dm, ic_dp,
kp_col_ip_0, kp_col_ip_1, kp_col_ip_2, kp_col_ip_3,
kp_row_op_0, kp_row_op_1, kp_row_op_2, kp_row_op_3,
lcd_b_0, lcd_b_1, lcd_b_2, lcd_b_3, lcd_b_4, lcd_b_5,
lcd_b_6, lcd_b_7, lcd_g_0, lcd_g_1, lcd_g_2, lcd_g_3,
lcd_g_4, lcd_g_5, lcd_g_6, lcd_g_7, lcd_hsync,
lcd_oe, lcd_pclk, lcd_r_0, lcd_r_1, lcd_r_2,
lcd_r_3, lcd_r_4, lcd_r_5, lcd_r_6, lcd_r_7,
lcd_vsync, mdmgpio0, mdmgpio1, mdmgpio2, mdmgpio3,
mdmgpio4, mdmgpio5, mdmgpio6, mdmgpio7, mdmgpio8,
mphi_data_0, mphi_data_1, mphi_data_2, mphi_data_3,
mphi_data_4, mphi_data_5, mphi_data_6, mphi_data_7,
mphi_data_8, mphi_data_9, mphi_data_10,
mphi_data_11, mphi_data_12, mphi_data_13,
mphi_data_14, mphi_data_15, mphi_ha0, mphi_hat0,
mphi_hat1, mphi_hce0_n, mphi_hce1_n, mphi_hrd_n,
mphi_hwr_n, mphi_run0, mphi_run1, mtx_scan_clk,
mtx_scan_data, nand_ad_0, nand_ad_1, nand_ad_2,
nand_ad_3, nand_ad_4, nand_ad_5, nand_ad_6,
nand_ad_7, nand_ale, nand_cen_0, nand_cen_1,
nand_cle, nand_oen, nand_rdy_0, nand_rdy_1,
nand_wen, nand_wp, pc1, pc2, pmu_int,
rfst2g_mtsloten3g, rgmii_0_rx_ctl, rgmii_0_rxc,
rgmii_0_rxd_0, rgmii_0_rxd_1, rgmii_0_rxd_2,
rgmii_0_rxd_3, rgmii_0_tx_ctl, rgmii_0_txc,
rgmii_0_txd_0, rgmii_0_txd_1, rgmii_0_txd_2,
rgmii_0_txd_3, rgmii_1_rx_ctl, rgmii_1_rxc,
rgmii_1_rxd_0, rgmii_1_rxd_1, rgmii_1_rxd_2,
rgmii_1_rxd_3, rgmii_1_tx_ctl, rgmii_1_txc,
rgmii_1_txd_0, rgmii_1_txd_1, rgmii_1_txd_2,
rgmii_1_txd_3, rgmii_gpio_0, rgmii_gpio_1,
rgmii_gpio_2, rgmii_gpio_3, rtxdata2g_txdata3g1,
rtxen2g_txdata3g2, rxdata3g0, rxdata3g1, rxdata3g2,
sdio1_clk, sdio1_cmd, sdio1_data_0, sdio1_data_1,
sdio1_data_2, sdio1_data_3, sdio4_clk, sdio4_cmd,
sdio4_data_0, sdio4_data_1, sdio4_data_2,
sdio4_data_3, sim_clk, sim_data, sim_det,
sim_resetn, sim2_clk, sim2_data, sim2_det,
sim2_resetn, sri_c, sri_d, sri_e, ssp_extclk,
ssp0_clk, ssp0_fs, ssp0_rxd, ssp0_txd, ssp2_clk,
ssp2_fs_0, ssp2_fs_1, ssp2_fs_2, ssp2_fs_3,
ssp2_rxd_0, ssp2_rxd_1, ssp2_txd_0, ssp2_txd_1,
ssp3_clk, ssp3_fs, ssp3_rxd, ssp3_txd, ssp4_clk,
ssp4_fs, ssp4_rxd, ssp4_txd, ssp5_clk, ssp5_fs,
ssp5_rxd, ssp5_txd, ssp6_clk, ssp6_fs, ssp6_rxd,
ssp6_txd, stat_1, stat_2, sysclken, traceclk,
tracedt00, tracedt01, tracedt02, tracedt03,
tracedt04, tracedt05, tracedt06, tracedt07,
tracedt08, tracedt09, tracedt10, tracedt11,
tracedt12, tracedt13, tracedt14, tracedt15,
txdata3g0, txpwrind, uartb1_ucts, uartb1_urts,
uartb1_urxd, uartb1_utxd, uartb2_urxd, uartb2_utxd,
uartb3_ucts, uartb3_urts, uartb3_urxd, uartb3_utxd,
uartb4_ucts, uartb4_urts, uartb4_urxd, uartb4_utxd ]
then:
properties:
drive-strength:
enum: [ 2, 4, 6, 8, 10, 12, 14, 16 ]
bias-disable: true
bias-pull-up: true
bias-pull-down: true
input-schmitt-enable: true
input-schmitt-disable: true
# Optional properties for I2C pins
- if:
properties:
pins:
contains:
enum: [ bsc1_scl, bsc1_sda, bsc2_scl, bsc2_sda, pmu_scl,
pmu_sda, vc_cam1_scl, vc_cam1_sda, vc_cam2_scl,
vc_cam2_sda, vc_cam3_scl, vc_cam3_sda ]
then:
properties:
bias-pull-up:
description:
There are 3 pull-up resistors (1.2k, 1.8k, 2.7k) available
in parallel for I2C pins.
enum: [ 568, 720, 831, 1080, 1200, 1800, 2700 ]
bias-disable: true
required:
- compatible
- reg
unevaluatedProperties: false
examples:
- |
pinctrl@35004800 {
compatible = "brcm,bcm11351-pinctrl";
reg = <0x35004800 0x430>;
dev-a-active-pins {
/* group node defining 1 standard pin */
std-grp0 {
pins = "gpio00";
function = "alt1";
input-schmitt-enable;
bias-disable;
slew-rate = <1>;
drive-strength = <4>;
};
/* group node defining 2 I2C pins */
i2c-grp0 {
pins = "bsc1_scl", "bsc1_sda";
function = "alt2";
bias-pull-up = <720>;
input-enable;
};
/* group node defining 2 HDMI pins */
hdmi-grp0 {
pins = "hdmi_scl", "hdmi_sda";
function = "alt3";
slew-rate = <1>;
};
};
};
...

4
Documentation/devicetree/bindings/pinctrl/cypress,cy8c95x0.yaml
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@ -51,6 +51,10 @@ properties:
description: description:
Optional power supply. Optional power supply.
reset-gpios:
description: GPIO connected to the XRES pin
maxItems: 1
patternProperties: patternProperties:
'-pins$': '-pins$':
type: object type: object

4
Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.yaml
View File

@ -135,7 +135,6 @@ additionalProperties:
- $ref: pinmux-node.yaml# - $ref: pinmux-node.yaml#
properties: properties:
phandle: true
function: true function: true
groups: true groups: true
pins: true pins: true
@ -147,8 +146,6 @@ additionalProperties:
additionalProperties: false additionalProperties: false
- type: object - type: object
properties:
phandle: true
additionalProperties: additionalProperties:
type: object type: object
allOf: allOf:
@ -156,7 +153,6 @@ additionalProperties:
- $ref: pinmux-node.yaml# - $ref: pinmux-node.yaml#
properties: properties:
phandle: true
function: true function: true
groups: true groups: true
pins: true pins: true

2
Documentation/devicetree/bindings/pinctrl/nvidia,tegra114-pinmux.yaml
View File

@ -22,8 +22,6 @@ properties:
patternProperties: patternProperties:
"^pinmux(-[a-z0-9-_]+)?$": "^pinmux(-[a-z0-9-_]+)?$":
type: object type: object
properties:
phandle: true
# pin groups # pin groups
additionalProperties: additionalProperties:

2
Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-pinmux.yaml
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@ -32,8 +32,6 @@ properties:
patternProperties: patternProperties:
"^pinmux(-[a-z0-9-_]+)?$": "^pinmux(-[a-z0-9-_]+)?$":
type: object type: object
properties:
phandle: true
# pin groups # pin groups
additionalProperties: additionalProperties:

2
Documentation/devicetree/bindings/pinctrl/nvidia,tegra194-pinmux.yaml
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@ -23,8 +23,6 @@ properties:
patternProperties: patternProperties:
"^pinmux(-[a-z0-9-_]+)?$": "^pinmux(-[a-z0-9-_]+)?$":
type: object type: object
properties:
phandle: true
# pin groups # pin groups
additionalProperties: additionalProperties:

2
Documentation/devicetree/bindings/pinctrl/nvidia,tegra20-pinmux.yaml
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@ -24,8 +24,6 @@ properties:
patternProperties: patternProperties:
"^pinmux(-[a-z0-9-_]+)?$": "^pinmux(-[a-z0-9-_]+)?$":
type: object type: object
properties:
phandle: true
# pin groups # pin groups
additionalProperties: additionalProperties:

2
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@ -22,8 +22,6 @@ properties:
patternProperties: patternProperties:
"^pinmux(-[a-z0-9-_]+)?$": "^pinmux(-[a-z0-9-_]+)?$":
type: object type: object
properties:
phandle: true
# pin groups # pin groups
additionalProperties: additionalProperties:

2
Documentation/devicetree/bindings/pinctrl/nvidia,tegra30-pinmux.yaml
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@ -22,8 +22,6 @@ properties:
patternProperties: patternProperties:
"^pinmux(-[a-z0-9-_]+)?$": "^pinmux(-[a-z0-9-_]+)?$":
type: object type: object
properties:
phandle: true
# pin groups # pin groups
additionalProperties: additionalProperties:

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@ -1,56 +0,0 @@
* Oxford Semiconductor OXNAS SoC Family Pin Controller
Please refer to pinctrl-bindings.txt, ../gpio/gpio.txt, and
../interrupt-controller/interrupts.txt for generic information regarding
pin controller, GPIO, and interrupt bindings.
OXNAS 'pin configuration node' is a node of a group of pins which can be
used for a specific device or function. This node represents configurations of
pins, optional function, and optional mux related configuration.
Required properties for pin controller node:
- compatible: "oxsemi,ox810se-pinctrl" or "oxsemi,ox820-pinctrl"
- oxsemi,sys-ctrl: a phandle to the system controller syscon node
Required properties for pin configuration sub-nodes:
- pins: List of pins to which the configuration applies.
Optional properties for pin configuration sub-nodes:
----------------------------------------------------
- function: Mux function for the specified pins.
- bias-pull-up: Enable weak pull-up.
Example:
pinctrl: pinctrl {
compatible = "oxsemi,ox810se-pinctrl";
/* Regmap for sys registers */
oxsemi,sys-ctrl = <&sys>;
pinctrl_uart2: pinctrl_uart2 {
uart2a {
pins = "gpio31";
function = "fct3";
};
uart2b {
pins = "gpio32";
function = "fct3";
};
};
};
uart2: serial@900000 {
compatible = "ns16550a";
reg = <0x900000 0x100000>;
clocks = <&sysclk>;
interrupts = <29>;
reg-shift = <0>;
fifo-size = <16>;
reg-io-width = <1>;
current-speed = <115200>;
no-loopback-test;
resets = <&reset 22>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
};

262
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@ -1,262 +0,0 @@
One-register-per-pin type device tree based pinctrl driver
Required properties:
- compatible : "pinctrl-single" or "pinconf-single".
"pinctrl-single" means that pinconf isn't supported.
"pinconf-single" means that generic pinconf is supported.
- reg : offset and length of the register set for the mux registers
- #pinctrl-cells : number of cells in addition to the index, set to 1
or 2 for pinctrl-single,pins and set to 2 for pinctrl-single,bits
- pinctrl-single,register-width : pinmux register access width in bits
- pinctrl-single,function-mask : mask of allowed pinmux function bits
in the pinmux register
Optional properties:
- pinctrl-single,function-off : function off mode for disabled state if
available and same for all registers; if not specified, disabling of
pin functions is ignored
- pinctrl-single,bit-per-mux : boolean to indicate that one register controls
more than one pin, for which "pinctrl-single,function-mask" property specifies
position mask of pin.
- pinctrl-single,drive-strength : array of value that are used to configure
drive strength in the pinmux register. They're value of drive strength
current and drive strength mask.
/* drive strength current, mask */
pinctrl-single,power-source = <0x30 0xf0>;
- pinctrl-single,bias-pullup : array of value that are used to configure the
input bias pullup in the pinmux register.
/* input, enabled pullup bits, disabled pullup bits, mask */
pinctrl-single,bias-pullup = <0 1 0 1>;
- pinctrl-single,bias-pulldown : array of value that are used to configure the
input bias pulldown in the pinmux register.
/* input, enabled pulldown bits, disabled pulldown bits, mask */
pinctrl-single,bias-pulldown = <2 2 0 2>;
* Two bits to control input bias pullup and pulldown: User should use
pinctrl-single,bias-pullup & pinctrl-single,bias-pulldown. One bit means
pullup, and the other one bit means pulldown.
* Three bits to control input bias enable, pullup and pulldown. User should
use pinctrl-single,bias-pullup & pinctrl-single,bias-pulldown. Input bias
enable bit should be included in pullup or pulldown bits.
* Although driver could set PIN_CONFIG_BIAS_DISABLE, there's no property as
pinctrl-single,bias-disable. Because pinctrl single driver could implement
it by calling pulldown, pullup disabled.
- pinctrl-single,input-schmitt : array of value that are used to configure
input schmitt in the pinmux register. In some silicons, there're two input
schmitt value (rising-edge & falling-edge) in the pinmux register.
/* input schmitt value, mask */
pinctrl-single,input-schmitt = <0x30 0x70>;
- pinctrl-single,input-schmitt-enable : array of value that are used to
configure input schmitt enable or disable in the pinmux register.
/* input, enable bits, disable bits, mask */
pinctrl-single,input-schmitt-enable = <0x30 0x40 0 0x70>;
- pinctrl-single,low-power-mode : array of value that are used to configure
low power mode of this pin. For some silicons, the low power mode will
control the output of the pin when the pad including the pin enter low
power mode.
/* low power mode value, mask */
pinctrl-single,low-power-mode = <0x288 0x388>;
- pinctrl-single,gpio-range : list of value that are used to configure a GPIO
range. They're value of subnode phandle, pin base in pinctrl device, pin
number in this range, GPIO function value of this GPIO range.
The number of parameters is depend on #pinctrl-single,gpio-range-cells
property.
/* pin base, nr pins & gpio function */
pinctrl-single,gpio-range = <&range 0 3 0>, <&range 3 9 1>;
- interrupt-controller : standard interrupt controller binding if using
interrupts for wake-up events for example. In this case pinctrl-single
is set up as a chained interrupt controller and the wake-up interrupts
can be requested by the drivers using request_irq().
- #interrupt-cells : standard interrupt binding if using interrupts
This driver assumes that there is only one register for each pin (unless the
pinctrl-single,bit-per-mux is set), and uses the common pinctrl bindings as
specified in the pinctrl-bindings.txt document in this directory.
The pin configuration nodes for pinctrl-single are specified as pinctrl
register offset and values using pinctrl-single,pins. Only the bits specified
in pinctrl-single,function-mask are updated.
When #pinctrl-cells = 1, then setting a pin for a device could be done with:
pinctrl-single,pins = <0xdc 0x118>;
Where 0xdc is the offset from the pinctrl register base address for the device
pinctrl register, and 0x118 contains the desired value of the pinctrl register.
When #pinctrl-cells = 2, then setting a pin for a device could be done with:
pinctrl-single,pins = <0xdc 0x30 0x07>;
Where 0x30 is the pin configuration value and 0x07 is the pin mux mode value.
These two values are OR'd together to produce the value stored at offset 0xdc.
See the device example and static board pins example below for more information.
In case when one register changes more than one pin's mux the
pinctrl-single,bits need to be used which takes three parameters:
pinctrl-single,bits = <0xdc 0x18 0xff>;
Where 0xdc is the offset from the pinctrl register base address for the
device pinctrl register, 0x18 is the desired value, and 0xff is the sub mask to
be used when applying this change to the register.
Optional sub-node: In case some pins could be configured as GPIO in the pinmux
register, those pins could be defined as a GPIO range. This sub-node is required
by pinctrl-single,gpio-range property.
Required properties in sub-node:
- #pinctrl-single,gpio-range-cells : the number of parameters after phandle in
pinctrl-single,gpio-range property.
range: gpio-range {
#pinctrl-single,gpio-range-cells = <3>;
};
Example:
/* SoC common file */
/* first controller instance for pins in core domain */
pmx_core: pinmux@4a100040 {
compatible = "pinctrl-single";
reg = <0x4a100040 0x0196>;
#address-cells = <1>;
#size-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
pinctrl-single,register-width = <16>;
pinctrl-single,function-mask = <0xffff>;
};
/* second controller instance for pins in wkup domain */
pmx_wkup: pinmux@4a31e040 {
compatible = "pinctrl-single";
reg = <0x4a31e040 0x0038>;
#address-cells = <1>;
#size-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
pinctrl-single,register-width = <16>;
pinctrl-single,function-mask = <0xffff>;
};
control_devconf0: pinmux@48002274 {
compatible = "pinctrl-single";
reg = <0x48002274 4>; /* Single register */
#address-cells = <1>;
#size-cells = <0>;
pinctrl-single,bit-per-mux;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0x5F>;
};
/* third controller instance for pins in gpio domain */
pmx_gpio: pinmux@d401e000 {
compatible = "pinconf-single";
reg = <0xd401e000 0x0330>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <7>;
/* sparse GPIO range could be supported */
pinctrl-single,gpio-range = <&range 0 3 0>, <&range 3 9 1>,
<&range 12 1 0>, <&range 13 29 1>,
<&range 43 1 0>, <&range 44 49 1>,
<&range 94 1 1>, <&range 96 2 1>;
range: gpio-range {
#pinctrl-single,gpio-range-cells = <3>;
};
};
/* board specific .dts file */
&pmx_core {
/*
* map all board specific static pins enabled by the pinctrl driver
* itself during the boot (or just set them up in the bootloader)
*/
pinctrl-names = "default";
pinctrl-0 = <&board_pins>;
board_pins: pinmux_board_pins {
pinctrl-single,pins = <
0x6c 0xf
0x6e 0xf
0x70 0xf
0x72 0xf
>;
};
uart0_pins: pinmux_uart0_pins {
pinctrl-single,pins = <
0x208 0 /* UART0_RXD (IOCFG138) */
0x20c 0 /* UART0_TXD (IOCFG139) */
>;
pinctrl-single,bias-pulldown = <0 2 2>;
pinctrl-single,bias-pullup = <0 1 1>;
};
/* map uart2 pins */
uart2_pins: pinmux_uart2_pins {
pinctrl-single,pins = <
0xd8 0x118
0xda 0
0xdc 0x118
0xde 0
>;
};
};
&control_devconf0 {
mcbsp1_pins: pinmux_mcbsp1_pins {
pinctrl-single,bits = <
0x00 0x18 0x18 /* FSR/CLKR signal from FSX/CLKX pin */
>;
};
mcbsp2_clks_pins: pinmux_mcbsp2_clks_pins {
pinctrl-single,bits = <
0x00 0x40 0x40 /* McBSP2 CLKS from McBSP_CLKS pin */
>;
};
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins>;
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&uart2_pins>;
};

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@ -0,0 +1,207 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/pinctrl-single.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Generic Pin Controller with a Single Register for One or More Pins
maintainers:
- Tony Lindgren <tony@atomide.com>
description:
Some pin controller devices use a single register for one or more pins. The
range of pin control registers can vary from one to many for each controller
instance. Some SoCs from Altera, Broadcom, HiSilicon, Ralink, and TI have this
kind of pin controller instances.
properties:
compatible:
oneOf:
- enum:
- pinctrl-single
- pinconf-single
- items:
- enum:
- ti,am437-padconf
- ti,am654-padconf
- ti,dra7-padconf
- ti,omap2420-padconf
- ti,omap2430-padconf
- ti,omap3-padconf
- ti,omap4-padconf
- ti,omap5-padconf
- const: pinctrl-single
reg:
maxItems: 1
interrupt-controller: true
'#interrupt-cells':
const: 1
'#address-cells':
const: 1
'#size-cells':
const: 0
'#pinctrl-cells':
description:
Number of cells. Usually 2, consisting of register offset, pin configuration
value, and pinmux mode. Some controllers may use 1 for just offset and value.
enum: [ 1, 2 ]
pinctrl-single,bit-per-mux:
description: Optional flag to indicate register controls more than one pin
type: boolean
pinctrl-single,function-mask:
description: Mask of the allowed register bits
$ref: /schemas/types.yaml#/definitions/uint32
pinctrl-single,function-off:
description: Optional function off mode for disabled state
$ref: /schemas/types.yaml#/definitions/uint32
pinctrl-single,register-width:
description: Width of pin specific bits in the register
$ref: /schemas/types.yaml#/definitions/uint32
enum: [ 8, 16, 32 ]
pinctrl-single,gpio-range:
description: Optional list of pin base, nr pins & gpio function
$ref: /schemas/types.yaml#/definitions/phandle-array
items:
- items:
- description: phandle of a gpio-range node
- description: pin base
- description: number of pins
- description: gpio function
'#gpio-range-cells':
description: No longer needed, may exist in older files for gpio-ranges
deprecated: true
const: 3
gpio-range:
description: Optional node for gpio range cells
type: object
additionalProperties: false
properties:
'#pinctrl-single,gpio-range-cells':
description: Number of gpio range cells
const: 3
$ref: /schemas/types.yaml#/definitions/uint32
patternProperties:
'-pins(-[0-9]+)?$|-pin$':
description:
Pin group node name using naming ending in -pins followed by an optional
instance number
type: object
additionalProperties: false
properties:
pinctrl-single,pins:
description:
Array of pins as described in pinmux-node.yaml for pinctrl-pin-array
$ref: /schemas/types.yaml#/definitions/uint32-array
pinctrl-single,bits:
description: Register bit configuration for pinctrl-single,bit-per-mux
$ref: /schemas/types.yaml#/definitions/uint32-array
items:
- description: register offset
- description: value
- description: pin bitmask in the register
pinctrl-single,bias-pullup:
description: Optional bias pull up configuration
$ref: /schemas/types.yaml#/definitions/uint32-array
items:
- description: input
- description: enabled pull up bits
- description: disabled pull up bits
- description: bias pull up mask
pinctrl-single,bias-pulldown:
description: Optional bias pull down configuration
$ref: /schemas/types.yaml#/definitions/uint32-array
items:
- description: input
- description: enabled pull down bits
- description: disabled pull down bits
- description: bias pull down mask
pinctrl-single,drive-strength:
description: Optional drive strength configuration
$ref: /schemas/types.yaml#/definitions/uint32-array
items:
- description: drive strength current
- description: drive strength mask
pinctrl-single,input-schmitt:
description: Optional input schmitt configuration
$ref: /schemas/types.yaml#/definitions/uint32-array
items:
- description: input
- description: enable bits
- description: disable bits
- description: input schmitt mask
pinctrl-single,low-power-mode:
description: Optional low power mode configuration
$ref: /schemas/types.yaml#/definitions/uint32-array
items:
- description: low power mode value
- description: low power mode mask
pinctrl-single,slew-rate:
description: Optional slew rate configuration
$ref: /schemas/types.yaml#/definitions/uint32-array
items:
- description: slew rate
- description: slew rate mask
allOf:
- $ref: pinctrl.yaml#
required:
- compatible
- reg
- pinctrl-single,register-width
additionalProperties: false
examples:
- |
soc {
#address-cells = <1>;
#size-cells = <1>;
pinmux@4a100040 {
compatible = "pinctrl-single";
reg = <0x4a100040 0x0196>;
#address-cells = <1>;
#size-cells = <0>;
#pinctrl-cells = <2>;
#interrupt-cells = <1>;
interrupt-controller;
pinctrl-single,register-width = <16>;
pinctrl-single,function-mask = <0xffff>;
pinctrl-single,gpio-range = <&range 0 3 0>;
range: gpio-range {
#pinctrl-single,gpio-range-cells = <3>;
};
uart2-pins {
pinctrl-single,pins =
<0xd8 0x118>,
<0xda 0>,
<0xdc 0x118>,
<0xde 0>;
};
};
};

8
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@ -26,6 +26,7 @@ properties:
- qcom,pm6350-gpio - qcom,pm6350-gpio
- qcom,pm7250b-gpio - qcom,pm7250b-gpio
- qcom,pm7325-gpio - qcom,pm7325-gpio
- qcom,pm7550ba-gpio
- qcom,pm8005-gpio - qcom,pm8005-gpio
- qcom,pm8008-gpio - qcom,pm8008-gpio
- qcom,pm8018-gpio - qcom,pm8018-gpio
@ -53,6 +54,8 @@ properties:
- qcom,pm8994-gpio - qcom,pm8994-gpio
- qcom,pm8998-gpio - qcom,pm8998-gpio
- qcom,pma8084-gpio - qcom,pma8084-gpio
- qcom,pmc8180-gpio
- qcom,pmc8180c-gpio
- qcom,pmi632-gpio - qcom,pmi632-gpio
- qcom,pmi8950-gpio - qcom,pmi8950-gpio
- qcom,pmi8994-gpio - qcom,pmi8994-gpio
@ -68,6 +71,7 @@ properties:
- qcom,pms405-gpio - qcom,pms405-gpio
- qcom,pmx55-gpio - qcom,pmx55-gpio
- qcom,pmx65-gpio - qcom,pmx65-gpio
- qcom,pmx75-gpio
- enum: - enum:
- qcom,spmi-gpio - qcom,spmi-gpio
@ -172,6 +176,7 @@ allOf:
compatible: compatible:
contains: contains:
enum: enum:
- qcom,pm7550ba-gpio
- qcom,pm8226-gpio - qcom,pm8226-gpio
- qcom,pm8350b-gpio - qcom,pm8350b-gpio
- qcom,pm8550ve-gpio - qcom,pm8550ve-gpio
@ -301,6 +306,7 @@ allOf:
contains: contains:
enum: enum:
- qcom,pmx65-gpio - qcom,pmx65-gpio
- qcom,pmx75-gpio
then: then:
properties: properties:
gpio-line-names: gpio-line-names:
@ -413,6 +419,7 @@ $defs:
- gpio1-gpio9 for pm6350 - gpio1-gpio9 for pm6350
- gpio1-gpio12 for pm7250b - gpio1-gpio12 for pm7250b
- gpio1-gpio10 for pm7325 - gpio1-gpio10 for pm7325
- gpio1-gpio8 for pm7550ba
- gpio1-gpio4 for pm8005 - gpio1-gpio4 for pm8005
- gpio1-gpio2 for pm8008 - gpio1-gpio2 for pm8008
- gpio1-gpio6 for pm8018 - gpio1-gpio6 for pm8018
@ -456,6 +463,7 @@ $defs:
- gpio1-gpio11 for pmx55 (holes on gpio3, gpio7, gpio10 - gpio1-gpio11 for pmx55 (holes on gpio3, gpio7, gpio10
and gpio11) and gpio11)
- gpio1-gpio16 for pmx65 - gpio1-gpio16 for pmx65
- gpio1-gpio16 for pmx75
items: items:
pattern: "^gpio([0-9]+)$" pattern: "^gpio([0-9]+)$"

5
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@ -17,11 +17,6 @@ properties:
compatible: compatible:
const: qcom,sc7280-lpass-lpi-pinctrl const: qcom,sc7280-lpass-lpi-pinctrl
qcom,adsp-bypass-mode:
description:
Tells ADSP is in bypass mode.
type: boolean
reg: reg:
maxItems: 2 maxItems: 2

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@ -0,0 +1,135 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,sm6115-lpass-lpi-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm SM6115 SoC LPASS LPI TLMM
maintainers:
- Konrad Dybcio <konradybcio@kernel.org>
- Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
description:
Top Level Mode Multiplexer pin controller in the Low Power Audio SubSystem
(LPASS) Low Power Island (LPI) of Qualcomm SM6115 SoC.
properties:
compatible:
const: qcom,sm6115-lpass-lpi-pinctrl
reg:
items:
- description: LPASS LPI TLMM Control and Status registers
- description: LPASS LPI MCC registers
clocks:
items:
- description: LPASS Audio voting clock
clock-names:
items:
- const: audio
gpio-controller: true
"#gpio-cells":
description: Specifying the pin number and flags, as defined in
include/dt-bindings/gpio/gpio.h
const: 2
gpio-ranges:
maxItems: 1
patternProperties:
"-state$":
oneOf:
- $ref: "#/$defs/qcom-sm6115-lpass-state"
- patternProperties:
"-pins$":
$ref: "#/$defs/qcom-sm6115-lpass-state"
additionalProperties: false
$defs:
qcom-sm6115-lpass-state:
type: object
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
$ref: /schemas/pinctrl/pincfg-node.yaml
properties:
pins:
description:
List of gpio pins affected by the properties specified in this
subnode.
items:
pattern: "^gpio([0-9]|1[0-8])$"
function:
enum: [ dmic01_clk, dmic01_data, dmic23_clk, dmic23_data, gpio, i2s1_clk,
i2s1_data, i2s1_ws, i2s2_clk, i2s2_data, i2s2_ws, i2s3_clk,
i2s3_data, i2s3_ws, qua_mi2s_data, qua_mi2s_sclk, qua_mi2s_ws,
swr_rx_clk, swr_rx_data, swr_tx_clk, swr_tx_data, wsa_mclk ]
description:
Specify the alternative function to be configured for the specified
pins.
drive-strength:
enum: [2, 4, 6, 8, 10, 12, 14, 16]
default: 2
description:
Selects the drive strength for the specified pins, in mA.
slew-rate:
enum: [0, 1, 2, 3]
default: 0
description: |
0: No adjustments
1: Higher Slew rate (faster edges)
2: Lower Slew rate (slower edges)
3: Reserved (No adjustments)
bias-bus-hold: true
bias-pull-down: true
bias-pull-up: true
bias-disable: true
input-enable: true
output-high: true
output-low: true
required:
- pins
- function
additionalProperties: false
allOf:
- $ref: pinctrl.yaml#
required:
- compatible
- reg
- clocks
- clock-names
- gpio-controller
- "#gpio-cells"
- gpio-ranges
additionalProperties: false
examples:
- |
#include <dt-bindings/sound/qcom,q6afe.h>
lpass_tlmm: pinctrl@a7c0000 {
compatible = "qcom,sm6115-lpass-lpi-pinctrl";
reg = <0x0a7c0000 0x20000>,
<0x0a950000 0x10000>;
clocks = <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
clock-names = "audio";
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&lpass_tlmm 0 0 19>;
};

143
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@ -0,0 +1,143 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,sm8350-lpass-lpi-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm SM8350 SoC LPASS LPI TLMM
maintainers:
- Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
- Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
description:
Top Level Mode Multiplexer pin controller in the Low Power Audio SubSystem
(LPASS) Low Power Island (LPI) of Qualcomm SM8350 SoC.
properties:
compatible:
const: qcom,sm8350-lpass-lpi-pinctrl
reg:
items:
- description: LPASS LPI TLMM Control and Status registers
- description: LPASS LPI MCC registers
clocks:
items:
- description: LPASS Core voting clock
- description: LPASS Audio voting clock
clock-names:
items:
- const: core
- const: audio
gpio-controller: true
"#gpio-cells":
description: Specifying the pin number and flags, as defined in
include/dt-bindings/gpio/gpio.h
const: 2
gpio-ranges:
maxItems: 1
patternProperties:
"-state$":
oneOf:
- $ref: "#/$defs/qcom-sm8350-lpass-state"
- patternProperties:
"-pins$":
$ref: "#/$defs/qcom-sm8350-lpass-state"
additionalProperties: false
$defs:
qcom-sm8350-lpass-state:
type: object
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
$ref: /schemas/pinctrl/pincfg-node.yaml
properties:
pins:
description:
List of gpio pins affected by the properties specified in this
subnode.
items:
pattern: "^gpio([0-9]|1[0-9]|2[0-2])$"
function:
enum: [ dmic1_clk, dmic1_data, dmic2_clk, dmic2_data, dmic3_clk,
dmic3_data, dmic4_clk, dmic4_data, ext_mclk1_a, ext_mclk1_b,
ext_mclk1_c, ext_mclk1_d, ext_mclk1_e, gpio, i2s0_clk,
i2s0_data, i2s0_ws, i2s1_clk, i2s1_data, i2s1_ws, i2s2_clk,
i2s2_data, i2s2_ws, i2s3_clk, i2s3_data, i2s3_ws, i2s4_clk,
i2s4_data, i2s4_ws, slimbus_clk, slimbus_data, swr_rx_clk,
swr_rx_data, swr_tx_clk, swr_tx_data, wsa_swr_clk,
wsa_swr_data, wsa2_swr_clk, wsa2_swr_data ]
description:
Specify the alternative function to be configured for the specified
pins.
drive-strength:
enum: [2, 4, 6, 8, 10, 12, 14, 16]
default: 2
description:
Selects the drive strength for the specified pins, in mA.
slew-rate:
enum: [0, 1, 2, 3]
default: 0
description: |
0: No adjustments
1: Higher Slew rate (faster edges)
2: Lower Slew rate (slower edges)
3: Reserved (No adjustments)
bias-bus-hold: true
bias-pull-down: true
bias-pull-up: true
bias-disable: true
input-enable: true
output-high: true
output-low: true
required:
- pins
- function
additionalProperties: false
allOf:
- $ref: pinctrl.yaml#
required:
- compatible
- reg
- clocks
- clock-names
- gpio-controller
- "#gpio-cells"
- gpio-ranges
additionalProperties: false
examples:
- |
#include <dt-bindings/sound/qcom,q6afe.h>
lpass_tlmm: pinctrl@33c0000 {
compatible = "qcom,sm8350-lpass-lpi-pinctrl";
reg = <0x033c0000 0x20000>,
<0x03550000 0x10000>;
clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
clock-names = "core", "audio";
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&lpass_tlmm 0 0 15>;
};

4
Documentation/devicetree/bindings/pinctrl/renesas,pfc.yaml
View File

@ -107,7 +107,6 @@ additionalProperties:
Client device subnodes use below standard properties. Client device subnodes use below standard properties.
properties: properties:
phandle: true
function: true function: true
groups: true groups: true
pins: true pins: true
@ -127,9 +126,6 @@ additionalProperties:
additionalProperties: false additionalProperties: false
- type: object - type: object
properties:
phandle: true
additionalProperties: additionalProperties:
$ref: "#/additionalProperties/anyOf/0" $ref: "#/additionalProperties/anyOf/0"

4
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View File

@ -108,7 +108,6 @@ additionalProperties:
Integers values in "pinmux" argument list are assembled as: Integers values in "pinmux" argument list are assembled as:
((PORT * 16 + PIN) | MUX_FUNC << 16) ((PORT * 16 + PIN) | MUX_FUNC << 16)
phandle: true
input-enable: true input-enable: true
output-enable: true output-enable: true
@ -118,9 +117,6 @@ additionalProperties:
additionalProperties: false additionalProperties: false
- type: object - type: object
properties:
phandle: true
additionalProperties: additionalProperties:
$ref: "#/additionalProperties/anyOf/0" $ref: "#/additionalProperties/anyOf/0"

61
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@ -37,40 +37,37 @@ properties:
gpio-ranges: gpio-ranges:
maxItems: 1 maxItems: 1
patternProperties: additionalProperties:
"^.*$": type: object
if:
type: object allOf:
then: - $ref: pincfg-node.yaml#
allOf: - $ref: pinmux-node.yaml#
- $ref: pincfg-node.yaml#
- $ref: pinmux-node.yaml# description:
The child nodes of the pin controller designate pins to be used for
specific peripheral functions or as GPIO.
A pin multiplexing sub-node describes how to configure a set of
(or a single) pin in some desired alternate function mode.
The values for the pinmux properties are a combination of port name,
pin number and the desired function index. Use the RZA2_PINMUX macro
located in include/dt-bindings/pinctrl/r7s9210-pinctrl.h to easily
define these.
For assigning GPIO pins, use the macro RZA2_PIN also in
to express the desired port pin.
properties:
pinmux:
description: description:
The child nodes of the pin controller designate pins to be used for Values are constructed from GPIO port number, pin number, and
specific peripheral functions or as GPIO. alternate function configuration number using the RZA2_PINMUX()
helper macro in r7s9210-pinctrl.h.
A pin multiplexing sub-node describes how to configure a set of required:
(or a single) pin in some desired alternate function mode. - pinmux
The values for the pinmux properties are a combination of port name,
pin number and the desired function index. Use the RZA2_PINMUX macro
located in include/dt-bindings/pinctrl/r7s9210-pinctrl.h to easily
define these.
For assigning GPIO pins, use the macro RZA2_PIN also in
to express the desired port pin.
properties: additionalProperties: false
phandle: true
pinmux:
description:
Values are constructed from GPIO port number, pin number, and
alternate function configuration number using the RZA2_PINMUX()
helper macro in r7s9210-pinctrl.h.
required:
- pinmux
additionalProperties: false
allOf: allOf:
- $ref: pinctrl.yaml# - $ref: pinctrl.yaml#
@ -82,8 +79,6 @@ required:
- '#gpio-cells' - '#gpio-cells'
- gpio-ranges - gpio-ranges
additionalProperties: false
examples: examples:
- | - |
#include <dt-bindings/pinctrl/r7s9210-pinctrl.h> #include <dt-bindings/pinctrl/r7s9210-pinctrl.h>

4
Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
View File

@ -83,7 +83,6 @@ additionalProperties:
Client device subnodes use below standard properties. Client device subnodes use below standard properties.
properties: properties:
phandle: true
pinmux: pinmux:
description: description:
Values are constructed from GPIO port number, pin number, and Values are constructed from GPIO port number, pin number, and
@ -106,9 +105,6 @@ additionalProperties:
line-name: true line-name: true
- type: object - type: object
properties:
phandle: true
additionalProperties: additionalProperties:
$ref: "#/additionalProperties/anyOf/0" $ref: "#/additionalProperties/anyOf/0"

4
Documentation/devicetree/bindings/pinctrl/renesas,rzn1-pinctrl.yaml
View File

@ -74,7 +74,6 @@ additionalProperties:
offset by 10. Additional identifiers are provided to specify the offset by 10. Additional identifiers are provided to specify the
MDIO source peripheral. MDIO source peripheral.
phandle: true
bias-disable: true bias-disable: true
bias-pull-up: bias-pull-up:
description: Pull up the pin with 50 kOhm description: Pull up the pin with 50 kOhm
@ -91,9 +90,6 @@ additionalProperties:
$ref: "#/additionalProperties/anyOf/0" $ref: "#/additionalProperties/anyOf/0"
- type: object - type: object
properties:
phandle: true
additionalProperties: additionalProperties:
$ref: "#/additionalProperties/anyOf/0" $ref: "#/additionalProperties/anyOf/0"

4
Documentation/devicetree/bindings/pinctrl/renesas,rzv2m-pinctrl.yaml
View File

@ -63,7 +63,6 @@ additionalProperties:
Client device subnodes use below standard properties. Client device subnodes use below standard properties.
properties: properties:
phandle: true
pinmux: pinmux:
description: description:
Values are constructed from GPIO port number, pin number, and Values are constructed from GPIO port number, pin number, and
@ -87,9 +86,6 @@ additionalProperties:
line-name: true line-name: true
- type: object - type: object
properties:
phandle: true
additionalProperties: additionalProperties:
$ref: "#/additionalProperties/anyOf/0" $ref: "#/additionalProperties/anyOf/0"

2
Documentation/devicetree/bindings/pinctrl/socionext,uniphier-pinctrl.yaml
View File

@ -32,7 +32,6 @@ additionalProperties:
- $ref: pinmux-node.yaml# - $ref: pinmux-node.yaml#
properties: properties:
phandle: true
function: true function: true
groups: true groups: true
pins: true pins: true
@ -49,7 +48,6 @@ additionalProperties:
- $ref: pinmux-node.yaml# - $ref: pinmux-node.yaml#
properties: properties:
phandle: true
function: true function: true
groups: true groups: true
pins: true pins: true

13
Documentation/devicetree/bindings/pinctrl/ti,omap-pinctrl.txt
View File

@ -1,13 +0,0 @@
OMAP Pinctrl definitions
Required properties:
- compatible : Should be one of:
"ti,omap2420-padconf" - OMAP2420 compatible pinctrl
"ti,omap2430-padconf" - OMAP2430 compatible pinctrl
"ti,omap3-padconf" - OMAP3 compatible pinctrl
"ti,omap4-padconf" - OMAP4 compatible pinctrl
"ti,omap5-padconf" - OMAP5 compatible pinctrl
"ti,dra7-padconf" - DRA7 compatible pinctrl
"ti,am437-padconf" - AM437x compatible pinctrl
See Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt for further details.

4
Documentation/devicetree/bindings/pinctrl/xlnx,zynqmp-pinctrl.yaml
View File

@ -273,6 +273,10 @@ patternProperties:
slew-rate: slew-rate:
enum: [0, 1] enum: [0, 1]
output-enable:
description:
This will internally disable the tri-state for MIO pins.
drive-strength: drive-strength:
description: description:
Selects the drive strength for MIO pins, in mA. Selects the drive strength for MIO pins, in mA.

2
arch/arm/boot/dts/st/ste-href520-tvk.dts
View File

@ -28,7 +28,7 @@
2900000 0x0>; 2900000 0x0>;
gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>; gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>;
enable-gpio = <&gpio2 14 GPIO_ACTIVE_HIGH>; enable-gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>;
enable-active-high; enable-active-high;
pinctrl-names = "default"; pinctrl-names = "default";

2
arch/arm/boot/dts/st/ste-hrefprev60-stuib.dts
View File

@ -27,7 +27,7 @@
2900000 0x0>; 2900000 0x0>;
gpios = <&tc3589x_gpio 18 GPIO_ACTIVE_HIGH>; gpios = <&tc3589x_gpio 18 GPIO_ACTIVE_HIGH>;
enable-gpio = <&tc3589x_gpio 17 GPIO_ACTIVE_HIGH>; enable-gpios = <&tc3589x_gpio 17 GPIO_ACTIVE_HIGH>;
enable-active-high; enable-active-high;
}; };

2
arch/arm/boot/dts/st/ste-hrefprev60-tvk.dts
View File

@ -27,7 +27,7 @@
2900000 0x0>; 2900000 0x0>;
gpios = <&tc3589x_gpio 18 GPIO_ACTIVE_HIGH>; gpios = <&tc3589x_gpio 18 GPIO_ACTIVE_HIGH>;
enable-gpio = <&tc3589x_gpio 17 GPIO_ACTIVE_HIGH>; enable-gpios = <&tc3589x_gpio 17 GPIO_ACTIVE_HIGH>;
enable-active-high; enable-active-high;
}; };
}; };

2
arch/arm/boot/dts/st/ste-hrefv60plus-stuib.dts
View File

@ -29,7 +29,7 @@
2900000 0x0>; 2900000 0x0>;
gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>; gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>;
enable-gpio = <&gpio5 9 GPIO_ACTIVE_HIGH>; enable-gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
enable-active-high; enable-active-high;
pinctrl-names = "default"; pinctrl-names = "default";

2
arch/arm/boot/dts/st/ste-hrefv60plus-tvk.dts
View File

@ -29,7 +29,7 @@
2900000 0x0>; 2900000 0x0>;
gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>; gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>;
enable-gpio = <&gpio5 9 GPIO_ACTIVE_HIGH>; enable-gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
enable-active-high; enable-active-high;
pinctrl-names = "default"; pinctrl-names = "default";

2
arch/arm/boot/dts/st/ste-snowball.dts
View File

@ -229,7 +229,7 @@
/* GPIO228 SD_SEL */ /* GPIO228 SD_SEL */
gpios = <&gpio7 4 GPIO_ACTIVE_HIGH>; gpios = <&gpio7 4 GPIO_ACTIVE_HIGH>;
/* GPIO217 MMC_EN */ /* GPIO217 MMC_EN */
enable-gpio = <&gpio6 25 GPIO_ACTIVE_HIGH>; enable-gpios = <&gpio6 25 GPIO_ACTIVE_HIGH>;
enable-active-high; enable-active-high;
regulator-min-microvolt = <1800000>; regulator-min-microvolt = <1800000>;

1
arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi
View File

@ -9,6 +9,7 @@
#include <dt-bindings/clock/g12a-aoclkc.h> #include <dt-bindings/clock/g12a-aoclkc.h>
#include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/amlogic,meson-g12a-gpio-intc.h>
#include <dt-bindings/reset/amlogic,meson-g12a-reset.h> #include <dt-bindings/reset/amlogic,meson-g12a-reset.h>
#include <dt-bindings/thermal/thermal.h> #include <dt-bindings/thermal/thermal.h>

2
arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts
View File

@ -343,7 +343,7 @@
interrupt-parent = <&gpio_intc>; interrupt-parent = <&gpio_intc>;
/* MAC_INTR on GPIOZ_14 */ /* MAC_INTR on GPIOZ_14 */
interrupts = <26 IRQ_TYPE_LEVEL_LOW>; interrupts = <IRQID_GPIOZ_14 IRQ_TYPE_LEVEL_LOW>;
}; };
}; };

2
arch/arm64/boot/dts/amlogic/meson-g12b-bananapi-cm4.dtsi
View File

@ -201,7 +201,7 @@
interrupt-parent = <&gpio_intc>; interrupt-parent = <&gpio_intc>;
/* MAC_INTR on GPIOZ_14 */ /* MAC_INTR on GPIOZ_14 */
interrupts = <26 IRQ_TYPE_LEVEL_LOW>; interrupts = <IRQID_GPIOZ_14 IRQ_TYPE_LEVEL_LOW>;
}; };
}; };

2
arch/arm64/boot/dts/amlogic/meson-g12b-bananapi.dtsi
View File

@ -325,7 +325,7 @@
interrupt-parent = <&gpio_intc>; interrupt-parent = <&gpio_intc>;
/* MAC_INTR on GPIOZ_14 */ /* MAC_INTR on GPIOZ_14 */
interrupts = <26 IRQ_TYPE_LEVEL_LOW>; interrupts = <IRQID_GPIOZ_14 IRQ_TYPE_LEVEL_LOW>;
}; };
}; };

4
arch/arm64/boot/dts/amlogic/meson-g12b-odroid-go-ultra.dts
View File

@ -380,7 +380,7 @@
compatible = "rockchip,rk818"; compatible = "rockchip,rk818";
reg = <0x1c>; reg = <0x1c>;
interrupt-parent = <&gpio_intc>; interrupt-parent = <&gpio_intc>;
interrupts = <7 IRQ_TYPE_LEVEL_LOW>; /* GPIOAO_7 */ interrupts = <IRQID_GPIOAO_7 IRQ_TYPE_LEVEL_LOW>; /* GPIOAO_7 */
#clock-cells = <1>; #clock-cells = <1>;
vcc1-supply = <&vdd_sys>; vcc1-supply = <&vdd_sys>;
@ -519,7 +519,7 @@
reg = <0x20>; reg = <0x20>;
interrupt-parent = <&gpio_intc>; interrupt-parent = <&gpio_intc>;
interrupts = <5 IRQ_TYPE_LEVEL_LOW>; /* GPIOAO_5 */ interrupts = <IRQID_GPIOAO_5 IRQ_TYPE_LEVEL_LOW>; /* GPIOAO_5 */
vcc1-supply = <&vdd_sys>; vcc1-supply = <&vdd_sys>;
vcc2-supply = <&vdd_sys>; vcc2-supply = <&vdd_sys>;

2
arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi
View File

@ -184,7 +184,7 @@
interrupt-parent = <&gpio_intc>; interrupt-parent = <&gpio_intc>;
/* MAC_INTR on GPIOZ_14 */ /* MAC_INTR on GPIOZ_14 */
interrupts = <26 IRQ_TYPE_LEVEL_LOW>; interrupts = <IRQID_GPIOZ_14 IRQ_TYPE_LEVEL_LOW>;
}; };
}; };

2
arch/arm64/boot/dts/amlogic/meson-g12b-w400.dtsi
View File

@ -269,7 +269,7 @@
interrupt-parent = <&gpio_intc>; interrupt-parent = <&gpio_intc>;
/* MAC_INTR on GPIOZ_14 */ /* MAC_INTR on GPIOZ_14 */
interrupts = <26 IRQ_TYPE_LEVEL_LOW>; interrupts = <IRQID_GPIOZ_14 IRQ_TYPE_LEVEL_LOW>;
}; };
}; };

2
arch/arm64/boot/dts/amlogic/meson-sm1-a95xf3-air-gbit.dts
View File

@ -99,7 +99,7 @@
interrupt-parent = <&gpio_intc>; interrupt-parent = <&gpio_intc>;
/* MAC_INTR on GPIOZ_14 */ /* MAC_INTR on GPIOZ_14 */
interrupts = <26 IRQ_TYPE_LEVEL_LOW>; interrupts = <IRQID_GPIOZ_14 IRQ_TYPE_LEVEL_LOW>;
}; };
}; };

4
arch/arm64/boot/dts/amlogic/meson-sm1-bananapi.dtsi
View File

@ -45,7 +45,7 @@
linux,code = <BTN_1>; linux,code = <BTN_1>;
gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_LOW>; gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_LOW>;
interrupt-parent = <&gpio_intc>; interrupt-parent = <&gpio_intc>;
interrupts = <3 IRQ_TYPE_EDGE_BOTH>; interrupts = <IRQID_GPIOAO_3 IRQ_TYPE_EDGE_BOTH>;
}; };
}; };
@ -217,7 +217,7 @@
interrupt-parent = <&gpio_intc>; interrupt-parent = <&gpio_intc>;
/* MAC_INTR on GPIOZ_14 */ /* MAC_INTR on GPIOZ_14 */
interrupts = <26 IRQ_TYPE_LEVEL_LOW>; interrupts = <IRQID_GPIOZ_14 IRQ_TYPE_LEVEL_LOW>;
}; };
}; };

2
arch/arm64/boot/dts/amlogic/meson-sm1-h96-max.dts
View File

@ -99,7 +99,7 @@
interrupt-parent = <&gpio_intc>; interrupt-parent = <&gpio_intc>;
/* MAC_INTR on GPIOZ_14 */ /* MAC_INTR on GPIOZ_14 */
interrupts = <26 IRQ_TYPE_LEVEL_LOW>; interrupts = <IRQID_GPIOZ_14 IRQ_TYPE_LEVEL_LOW>;
}; };
}; };

2
arch/arm64/boot/dts/amlogic/meson-sm1-odroid.dtsi
View File

@ -282,7 +282,7 @@
interrupt-parent = <&gpio_intc>; interrupt-parent = <&gpio_intc>;
/* MAC_INTR on GPIOZ_14 */ /* MAC_INTR on GPIOZ_14 */
interrupts = <26 IRQ_TYPE_LEVEL_LOW>; interrupts = <IRQID_GPIOZ_14 IRQ_TYPE_LEVEL_LOW>;
}; };
}; };

12
arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts
View File

@ -53,7 +53,7 @@
linux,code = <BTN_0>; linux,code = <BTN_0>;
gpios = <&gpio GPIOH_6 GPIO_ACTIVE_LOW>; gpios = <&gpio GPIOH_6 GPIO_ACTIVE_LOW>;
interrupt-parent = <&gpio_intc>; interrupt-parent = <&gpio_intc>;
interrupts = <34 IRQ_TYPE_EDGE_BOTH>; interrupts = <IRQID_GPIOH_6 IRQ_TYPE_EDGE_BOTH>;
}; };
key-2 { key-2 {
@ -61,7 +61,7 @@
linux,code = <BTN_1>; linux,code = <BTN_1>;
gpios = <&gpio GPIOH_7 GPIO_ACTIVE_LOW>; gpios = <&gpio GPIOH_7 GPIO_ACTIVE_LOW>;
interrupt-parent = <&gpio_intc>; interrupt-parent = <&gpio_intc>;
interrupts = <35 IRQ_TYPE_EDGE_BOTH>; interrupts = <IRQID_GPIOH_7 IRQ_TYPE_EDGE_BOTH>;
}; };
key-3 { key-3 {
@ -69,7 +69,7 @@
linux,code = <BTN_2>; linux,code = <BTN_2>;
gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>; gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>;
interrupt-parent = <&gpio_intc>; interrupt-parent = <&gpio_intc>;
interrupts = <2 IRQ_TYPE_EDGE_BOTH>; interrupts = <IRQID_GPIOAO_2 IRQ_TYPE_EDGE_BOTH>;
}; };
key-mic-mute { key-mic-mute {
@ -78,7 +78,7 @@
linux,input-type = <EV_SW>; linux,input-type = <EV_SW>;
gpios = <&gpio_ao GPIOE_2 GPIO_ACTIVE_LOW>; gpios = <&gpio_ao GPIOE_2 GPIO_ACTIVE_LOW>;
interrupt-parent = <&gpio_intc>; interrupt-parent = <&gpio_intc>;
interrupts = <99 IRQ_TYPE_EDGE_BOTH>; interrupts = <IRQID_GPIOE_2 IRQ_TYPE_EDGE_BOTH>;
}; };
key-power { key-power {
@ -86,7 +86,7 @@
linux,code = <KEY_POWER>; linux,code = <KEY_POWER>;
gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_LOW>; gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_LOW>;
interrupt-parent = <&gpio_intc>; interrupt-parent = <&gpio_intc>;
interrupts = <3 IRQ_TYPE_EDGE_BOTH>; interrupts = <IRQID_GPIOAO_3 IRQ_TYPE_EDGE_BOTH>;
}; };
}; };
@ -582,7 +582,7 @@
bluetooth { bluetooth {
compatible = "brcm,bcm43438-bt"; compatible = "brcm,bcm43438-bt";
interrupt-parent = <&gpio_intc>; interrupt-parent = <&gpio_intc>;
interrupts = <95 IRQ_TYPE_LEVEL_HIGH>; interrupts = <IRQID_GPIOX_18 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "host-wakeup"; interrupt-names = "host-wakeup";
shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>;
max-speed = <2000000>; max-speed = <2000000>;

2
arch/arm64/boot/dts/amlogic/meson-sm1-x96-air-gbit.dts
View File

@ -99,7 +99,7 @@
interrupt-parent = <&gpio_intc>; interrupt-parent = <&gpio_intc>;
/* MAC_INTR on GPIOZ_14 */ /* MAC_INTR on GPIOZ_14 */
interrupts = <26 IRQ_TYPE_LEVEL_LOW>; interrupts = <IRQID_GPIOZ_14 IRQ_TYPE_LEVEL_LOW>;
}; };
}; };

49
drivers/firmware/xilinx/zynqmp.c
View File

@ -340,6 +340,8 @@ int zynqmp_pm_invoke_fn(u32 pm_api_id, u32 arg0, u32 arg1,
static u32 pm_api_version; static u32 pm_api_version;
static u32 pm_tz_version; static u32 pm_tz_version;
static u32 pm_family_code;
static u32 pm_sub_family_code;
int zynqmp_pm_register_sgi(u32 sgi_num, u32 reset) int zynqmp_pm_register_sgi(u32 sgi_num, u32 reset)
{ {
@ -405,6 +407,39 @@ int zynqmp_pm_get_chipid(u32 *idcode, u32 *version)
} }
EXPORT_SYMBOL_GPL(zynqmp_pm_get_chipid); EXPORT_SYMBOL_GPL(zynqmp_pm_get_chipid);
/**
* zynqmp_pm_get_family_info() - Get family info of platform
* @family: Returned family code value
* @subfamily: Returned sub-family code value
*
* Return: Returns status, either success or error+reason
*/
static int zynqmp_pm_get_family_info(u32 *family, u32 *subfamily)
{
u32 ret_payload[PAYLOAD_ARG_CNT];
u32 idcode;
int ret;
/* Check is family or sub-family code already received */
if (pm_family_code && pm_sub_family_code) {
*family = pm_family_code;
*subfamily = pm_sub_family_code;
return 0;
}
ret = zynqmp_pm_invoke_fn(PM_GET_CHIPID, 0, 0, 0, 0, ret_payload);
if (ret < 0)
return ret;
idcode = ret_payload[1];
pm_family_code = FIELD_GET(FAMILY_CODE_MASK, idcode);
pm_sub_family_code = FIELD_GET(SUB_FAMILY_CODE_MASK, idcode);
*family = pm_family_code;
*subfamily = pm_sub_family_code;
return 0;
}
/** /**
* zynqmp_pm_get_trustzone_version() - Get secure trustzone firmware version * zynqmp_pm_get_trustzone_version() - Get secure trustzone firmware version
* @version: Returned version value * @version: Returned version value
@ -1122,6 +1157,15 @@ EXPORT_SYMBOL_GPL(zynqmp_pm_pinctrl_get_config);
int zynqmp_pm_pinctrl_set_config(const u32 pin, const u32 param, int zynqmp_pm_pinctrl_set_config(const u32 pin, const u32 param,
u32 value) u32 value)
{ {
int ret;
if (pm_family_code == ZYNQMP_FAMILY_CODE &&
param == PM_PINCTRL_CONFIG_TRI_STATE) {
ret = zynqmp_pm_feature(PM_PINCTRL_CONFIG_PARAM_SET);
if (ret < PM_PINCTRL_PARAM_SET_VERSION)
return -EOPNOTSUPP;
}
return zynqmp_pm_invoke_fn(PM_PINCTRL_CONFIG_PARAM_SET, pin, return zynqmp_pm_invoke_fn(PM_PINCTRL_CONFIG_PARAM_SET, pin,
param, value, 0, NULL); param, value, 0, NULL);
} }
@ -1920,6 +1964,11 @@ static int zynqmp_firmware_probe(struct platform_device *pdev)
pr_info("%s Platform Management API v%d.%d\n", __func__, pr_info("%s Platform Management API v%d.%d\n", __func__,
pm_api_version >> 16, pm_api_version & 0xFFFF); pm_api_version >> 16, pm_api_version & 0xFFFF);
/* Get the Family code and sub family code of platform */
ret = zynqmp_pm_get_family_info(&pm_family_code, &pm_sub_family_code);
if (ret < 0)
return ret;
/* Check trustzone version number */ /* Check trustzone version number */
ret = zynqmp_pm_get_trustzone_version(&pm_tz_version); ret = zynqmp_pm_get_trustzone_version(&pm_tz_version);
if (ret) if (ret)

11
drivers/pinctrl/Kconfig
View File

@ -355,17 +355,6 @@ config PINCTRL_OCELOT
If conpiled as a module, the module name will be pinctrl-ocelot. If conpiled as a module, the module name will be pinctrl-ocelot.
config PINCTRL_OXNAS
bool
depends on OF
select PINMUX
select PINCONF
select GENERIC_PINCONF
select GPIOLIB
select OF_GPIO
select GPIOLIB_IRQCHIP
select MFD_SYSCON
config PINCTRL_PALMAS config PINCTRL_PALMAS
tristate "Pinctrl driver for the PALMAS Series MFD devices" tristate "Pinctrl driver for the PALMAS Series MFD devices"
depends on OF && MFD_PALMAS depends on OF && MFD_PALMAS

1
drivers/pinctrl/Makefile
View File

@ -38,7 +38,6 @@ obj-$(CONFIG_PINCTRL_MCP23S08) += pinctrl-mcp23s08.o
obj-$(CONFIG_PINCTRL_MICROCHIP_SGPIO) += pinctrl-microchip-sgpio.o obj-$(CONFIG_PINCTRL_MICROCHIP_SGPIO) += pinctrl-microchip-sgpio.o
obj-$(CONFIG_PINCTRL_MLXBF3) += pinctrl-mlxbf3.o obj-$(CONFIG_PINCTRL_MLXBF3) += pinctrl-mlxbf3.o
obj-$(CONFIG_PINCTRL_OCELOT) += pinctrl-ocelot.o obj-$(CONFIG_PINCTRL_OCELOT) += pinctrl-ocelot.o
obj-$(CONFIG_PINCTRL_OXNAS) += pinctrl-oxnas.o
obj-$(CONFIG_PINCTRL_PALMAS) += pinctrl-palmas.o obj-$(CONFIG_PINCTRL_PALMAS) += pinctrl-palmas.o
obj-$(CONFIG_PINCTRL_PIC32) += pinctrl-pic32.o obj-$(CONFIG_PINCTRL_PIC32) += pinctrl-pic32.o
obj-$(CONFIG_PINCTRL_PISTACHIO) += pinctrl-pistachio.o obj-$(CONFIG_PINCTRL_PISTACHIO) += pinctrl-pistachio.o

10
drivers/pinctrl/bcm/pinctrl-iproc-gpio.c
View File

@ -21,8 +21,8 @@
#include <linux/io.h> #include <linux/io.h>
#include <linux/ioport.h> #include <linux/ioport.h>
#include <linux/kernel.h> #include <linux/kernel.h>
#include <linux/of_device.h> #include <linux/of.h>
#include <linux/of_irq.h> #include <linux/platform_device.h>
#include <linux/seq_file.h> #include <linux/seq_file.h>
#include <linux/slab.h> #include <linux/slab.h>
@ -891,10 +891,8 @@ static int iproc_gpio_probe(struct platform_device *pdev)
} }
ret = gpiochip_add_data(gc, chip); ret = gpiochip_add_data(gc, chip);
if (ret < 0) { if (ret < 0)
dev_err(dev, "unable to add GPIO chip\n"); return dev_err_probe(dev, ret, "unable to add GPIO chip\n");
return ret;
}
if (!no_pinconf) { if (!no_pinconf) {
ret = iproc_gpio_register_pinconf(chip); ret = iproc_gpio_register_pinconf(chip);

11
drivers/pinctrl/bcm/pinctrl-nsp-gpio.c
View File

@ -15,12 +15,11 @@
#include <linux/io.h> #include <linux/io.h>
#include <linux/ioport.h> #include <linux/ioport.h>
#include <linux/kernel.h> #include <linux/kernel.h>
#include <linux/of_address.h> #include <linux/of.h>
#include <linux/of_device.h>
#include <linux/of_irq.h>
#include <linux/pinctrl/pinconf.h> #include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinconf-generic.h> #include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinctrl.h> #include <linux/pinctrl/pinctrl.h>
#include <linux/platform_device.h>
#include <linux/slab.h> #include <linux/slab.h>
#include "../pinctrl-utils.h" #include "../pinctrl-utils.h"
@ -686,10 +685,8 @@ static int nsp_gpio_probe(struct platform_device *pdev)
} }
ret = devm_gpiochip_add_data(dev, gc, chip); ret = devm_gpiochip_add_data(dev, gc, chip);
if (ret < 0) { if (ret < 0)
dev_err(dev, "unable to add GPIO chip\n"); return dev_err_probe(dev, ret, "unable to add GPIO chip\n");
return ret;
}
ret = nsp_gpio_register_pinconf(chip); ret = nsp_gpio_register_pinconf(chip);
if (ret) { if (ret) {

3
drivers/pinctrl/berlin/pinctrl-as370.c
View File

@ -341,8 +341,7 @@ static int as370_pinctrl_probe(struct platform_device *pdev)
if (!rmconfig) if (!rmconfig)
return -ENOMEM; return -ENOMEM;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0); base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
base = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(base)) if (IS_ERR(base))
return PTR_ERR(base); return PTR_ERR(base);

20
drivers/pinctrl/core.c
View File

@ -205,6 +205,7 @@ static int pinctrl_register_one_pin(struct pinctrl_dev *pctldev,
const struct pinctrl_pin_desc *pin) const struct pinctrl_pin_desc *pin)
{ {
struct pin_desc *pindesc; struct pin_desc *pindesc;
int error;
pindesc = pin_desc_get(pctldev, pin->number); pindesc = pin_desc_get(pctldev, pin->number);
if (pindesc) { if (pindesc) {
@ -226,18 +227,25 @@ static int pinctrl_register_one_pin(struct pinctrl_dev *pctldev,
} else { } else {
pindesc->name = kasprintf(GFP_KERNEL, "PIN%u", pin->number); pindesc->name = kasprintf(GFP_KERNEL, "PIN%u", pin->number);
if (!pindesc->name) { if (!pindesc->name) {
kfree(pindesc); error = -ENOMEM;
return -ENOMEM; goto failed;
} }
pindesc->dynamic_name = true; pindesc->dynamic_name = true;
} }
pindesc->drv_data = pin->drv_data; pindesc->drv_data = pin->drv_data;
radix_tree_insert(&pctldev->pin_desc_tree, pin->number, pindesc); error = radix_tree_insert(&pctldev->pin_desc_tree, pin->number, pindesc);
if (error)
goto failed;
pr_debug("registered pin %d (%s) on %s\n", pr_debug("registered pin %d (%s) on %s\n",
pin->number, pindesc->name, pctldev->desc->name); pin->number, pindesc->name, pctldev->desc->name);
return 0; return 0;
failed:
kfree(pindesc);
return error;
} }
static int pinctrl_register_pins(struct pinctrl_dev *pctldev, static int pinctrl_register_pins(struct pinctrl_dev *pctldev,
@ -633,7 +641,7 @@ int pinctrl_generic_add_group(struct pinctrl_dev *pctldev, const char *name,
int *pins, int num_pins, void *data) int *pins, int num_pins, void *data)
{ {
struct group_desc *group; struct group_desc *group;
int selector; int selector, error;
if (!name) if (!name)
return -EINVAL; return -EINVAL;
@ -653,7 +661,9 @@ int pinctrl_generic_add_group(struct pinctrl_dev *pctldev, const char *name,
group->num_pins = num_pins; group->num_pins = num_pins;
group->data = data; group->data = data;
radix_tree_insert(&pctldev->pin_group_tree, selector, group); error = radix_tree_insert(&pctldev->pin_group_tree, selector, group);
if (error)
return error;
pctldev->num_groups++; pctldev->num_groups++;

2
drivers/pinctrl/freescale/pinctrl-imx.c
View File

@ -14,7 +14,7 @@
#include <linux/module.h> #include <linux/module.h>
#include <linux/of.h> #include <linux/of.h>
#include <linux/of_address.h> #include <linux/of_address.h>
#include <linux/of_device.h> #include <linux/platform_device.h>
#include <linux/regmap.h> #include <linux/regmap.h>
#include <linux/seq_file.h> #include <linux/seq_file.h>
#include <linux/slab.h> #include <linux/slab.h>

3
drivers/pinctrl/freescale/pinctrl-imx1-core.c
View File

@ -15,7 +15,8 @@
#include <linux/init.h> #include <linux/init.h>
#include <linux/io.h> #include <linux/io.h>
#include <linux/of.h> #include <linux/of.h>
#include <linux/of_device.h> #include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/seq_file.h> #include <linux/seq_file.h>
#include <linux/slab.h> #include <linux/slab.h>

3
drivers/pinctrl/freescale/pinctrl-imx23.c
View File

@ -6,7 +6,8 @@
// Copyright 2012 Freescale Semiconductor, Inc. // Copyright 2012 Freescale Semiconductor, Inc.
#include <linux/init.h> #include <linux/init.h>
#include <linux/of_device.h> #include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h> #include <linux/pinctrl/pinctrl.h>
#include "pinctrl-mxs.h" #include "pinctrl-mxs.h"

4
drivers/pinctrl/freescale/pinctrl-imx25.c
View File

@ -14,8 +14,8 @@
#include <linux/err.h> #include <linux/err.h>
#include <linux/init.h> #include <linux/init.h>
#include <linux/io.h> #include <linux/io.h>
#include <linux/of.h> #include <linux/mod_devicetable.h>
#include <linux/of_device.h> #include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h> #include <linux/pinctrl/pinctrl.h>
#include "pinctrl-imx.h" #include "pinctrl-imx.h"

4
drivers/pinctrl/freescale/pinctrl-imx27.c
View File

@ -9,8 +9,8 @@
#include <linux/err.h> #include <linux/err.h>
#include <linux/init.h> #include <linux/init.h>
#include <linux/io.h> #include <linux/io.h>
#include <linux/of.h> #include <linux/mod_devicetable.h>
#include <linux/of_device.h> #include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h> #include <linux/pinctrl/pinctrl.h>
#include "pinctrl-imx1.h" #include "pinctrl-imx1.h"

3
drivers/pinctrl/freescale/pinctrl-imx28.c
View File

@ -6,7 +6,8 @@
// Copyright 2012 Freescale Semiconductor, Inc. // Copyright 2012 Freescale Semiconductor, Inc.
#include <linux/init.h> #include <linux/init.h>
#include <linux/of_device.h> #include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h> #include <linux/pinctrl/pinctrl.h>
#include "pinctrl-mxs.h" #include "pinctrl-mxs.h"

4
drivers/pinctrl/freescale/pinctrl-imx35.c
View File

@ -12,8 +12,8 @@
#include <linux/err.h> #include <linux/err.h>
#include <linux/init.h> #include <linux/init.h>
#include <linux/io.h> #include <linux/io.h>
#include <linux/of.h> #include <linux/mod_devicetable.h>
#include <linux/of_device.h> #include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h> #include <linux/pinctrl/pinctrl.h>
#include "pinctrl-imx.h" #include "pinctrl-imx.h"

4
drivers/pinctrl/freescale/pinctrl-imx50.c
View File

@ -9,8 +9,8 @@
#include <linux/err.h> #include <linux/err.h>
#include <linux/init.h> #include <linux/init.h>
#include <linux/io.h> #include <linux/io.h>
#include <linux/of.h> #include <linux/mod_devicetable.h>
#include <linux/of_device.h> #include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h> #include <linux/pinctrl/pinctrl.h>
#include "pinctrl-imx.h" #include "pinctrl-imx.h"

4
drivers/pinctrl/freescale/pinctrl-imx51.c
View File

@ -10,8 +10,8 @@
#include <linux/err.h> #include <linux/err.h>
#include <linux/init.h> #include <linux/init.h>
#include <linux/io.h> #include <linux/io.h>
#include <linux/of.h> #include <linux/mod_devicetable.h>
#include <linux/of_device.h> #include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h> #include <linux/pinctrl/pinctrl.h>
#include "pinctrl-imx.h" #include "pinctrl-imx.h"

4
drivers/pinctrl/freescale/pinctrl-imx53.c
View File

@ -10,8 +10,8 @@
#include <linux/err.h> #include <linux/err.h>
#include <linux/init.h> #include <linux/init.h>
#include <linux/io.h> #include <linux/io.h>
#include <linux/of.h> #include <linux/mod_devicetable.h>
#include <linux/of_device.h> #include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h> #include <linux/pinctrl/pinctrl.h>
#include "pinctrl-imx.h" #include "pinctrl-imx.h"

4
drivers/pinctrl/freescale/pinctrl-imx6dl.c
View File

@ -8,8 +8,8 @@
#include <linux/err.h> #include <linux/err.h>
#include <linux/init.h> #include <linux/init.h>
#include <linux/io.h> #include <linux/io.h>
#include <linux/of.h> #include <linux/mod_devicetable.h>
#include <linux/of_device.h> #include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h> #include <linux/pinctrl/pinctrl.h>
#include "pinctrl-imx.h" #include "pinctrl-imx.h"

4
drivers/pinctrl/freescale/pinctrl-imx6q.c
View File

@ -10,8 +10,8 @@
#include <linux/err.h> #include <linux/err.h>
#include <linux/init.h> #include <linux/init.h>
#include <linux/io.h> #include <linux/io.h>
#include <linux/of.h> #include <linux/mod_devicetable.h>
#include <linux/of_device.h> #include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h> #include <linux/pinctrl/pinctrl.h>
#include "pinctrl-imx.h" #include "pinctrl-imx.h"

4
drivers/pinctrl/freescale/pinctrl-imx6sl.c
View File

@ -8,8 +8,8 @@
#include <linux/err.h> #include <linux/err.h>
#include <linux/init.h> #include <linux/init.h>
#include <linux/io.h> #include <linux/io.h>
#include <linux/of.h> #include <linux/mod_devicetable.h>
#include <linux/of_device.h> #include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h> #include <linux/pinctrl/pinctrl.h>
#include "pinctrl-imx.h" #include "pinctrl-imx.h"

4
drivers/pinctrl/freescale/pinctrl-imx6sll.c
View File

@ -7,8 +7,8 @@
#include <linux/init.h> #include <linux/init.h>
#include <linux/io.h> #include <linux/io.h>
#include <linux/module.h> #include <linux/module.h>
#include <linux/of.h> #include <linux/mod_devicetable.h>
#include <linux/of_device.h> #include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h> #include <linux/pinctrl/pinctrl.h>
#include "pinctrl-imx.h" #include "pinctrl-imx.h"

4
drivers/pinctrl/freescale/pinctrl-imx6sx.c
View File

@ -8,8 +8,8 @@
#include <linux/err.h> #include <linux/err.h>
#include <linux/init.h> #include <linux/init.h>
#include <linux/io.h> #include <linux/io.h>
#include <linux/of.h> #include <linux/mod_devicetable.h>
#include <linux/of_device.h> #include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h> #include <linux/pinctrl/pinctrl.h>
#include "pinctrl-imx.h" #include "pinctrl-imx.h"

2
drivers/pinctrl/freescale/pinctrl-imx6ul.c
View File

@ -9,7 +9,7 @@
#include <linux/init.h> #include <linux/init.h>
#include <linux/io.h> #include <linux/io.h>
#include <linux/of.h> #include <linux/of.h>
#include <linux/of_device.h> #include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h> #include <linux/pinctrl/pinctrl.h>
#include "pinctrl-imx.h" #include "pinctrl-imx.h"

2
drivers/pinctrl/freescale/pinctrl-imx7d.c
View File

@ -9,7 +9,7 @@
#include <linux/init.h> #include <linux/init.h>
#include <linux/io.h> #include <linux/io.h>
#include <linux/of.h> #include <linux/of.h>
#include <linux/of_device.h> #include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h> #include <linux/pinctrl/pinctrl.h>
#include "pinctrl-imx.h" #include "pinctrl-imx.h"

5
drivers/pinctrl/freescale/pinctrl-imx7ulp.c
View File

@ -8,9 +8,8 @@
#include <linux/err.h> #include <linux/err.h>
#include <linux/init.h> #include <linux/init.h>
#include <linux/io.h> #include <linux/io.h>
#include <linux/module.h> #include <linux/mod_devicetable.h>
#include <linux/of.h> #include <linux/platform_device.h>
#include <linux/of_device.h>
#include <linux/pinctrl/pinctrl.h> #include <linux/pinctrl/pinctrl.h>
#include "pinctrl-imx.h" #include "pinctrl-imx.h"

4
drivers/pinctrl/freescale/pinctrl-imx8dxl.c
View File

@ -8,10 +8,10 @@
#include <linux/firmware/imx/sci.h> #include <linux/firmware/imx/sci.h>
#include <linux/init.h> #include <linux/init.h>
#include <linux/io.h> #include <linux/io.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h> #include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/pinctrl.h> #include <linux/pinctrl/pinctrl.h>
#include <linux/platform_device.h>
#include "pinctrl-imx.h" #include "pinctrl-imx.h"

2
drivers/pinctrl/freescale/pinctrl-imx8mm.c
View File

@ -6,7 +6,7 @@
#include <linux/err.h> #include <linux/err.h>
#include <linux/init.h> #include <linux/init.h>
#include <linux/module.h> #include <linux/module.h>
#include <linux/of_device.h> #include <linux/of.h>
#include <linux/pinctrl/pinctrl.h> #include <linux/pinctrl/pinctrl.h>
#include <linux/platform_device.h> #include <linux/platform_device.h>

4
drivers/pinctrl/freescale/pinctrl-imx8mq.c
View File

@ -8,10 +8,10 @@
#include <linux/err.h> #include <linux/err.h>
#include <linux/init.h> #include <linux/init.h>
#include <linux/io.h> #include <linux/io.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h> #include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/pinctrl.h> #include <linux/pinctrl/pinctrl.h>
#include <linux/platform_device.h>
#include "pinctrl-imx.h" #include "pinctrl-imx.h"

3
drivers/pinctrl/freescale/pinctrl-imx8qxp.c
View File

@ -10,10 +10,11 @@
#include <linux/firmware/imx/sci.h> #include <linux/firmware/imx/sci.h>
#include <linux/init.h> #include <linux/init.h>
#include <linux/io.h> #include <linux/io.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h> #include <linux/module.h>
#include <linux/of.h> #include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/pinctrl.h> #include <linux/pinctrl/pinctrl.h>
#include <linux/platform_device.h>
#include "pinctrl-imx.h" #include "pinctrl-imx.h"

4
drivers/pinctrl/freescale/pinctrl-imx8ulp.c
View File

@ -6,10 +6,10 @@
#include <linux/err.h> #include <linux/err.h>
#include <linux/init.h> #include <linux/init.h>
#include <linux/io.h> #include <linux/io.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h> #include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/pinctrl.h> #include <linux/pinctrl/pinctrl.h>
#include <linux/platform_device.h>
#include "pinctrl-imx.h" #include "pinctrl-imx.h"

4
drivers/pinctrl/freescale/pinctrl-imx93.c
View File

@ -6,10 +6,10 @@
#include <linux/err.h> #include <linux/err.h>
#include <linux/init.h> #include <linux/init.h>
#include <linux/io.h> #include <linux/io.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h> #include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/pinctrl.h> #include <linux/pinctrl/pinctrl.h>
#include <linux/platform_device.h>
#include "pinctrl-imx.h" #include "pinctrl-imx.h"

2
drivers/pinctrl/freescale/pinctrl-imxrt1050.c
View File

@ -6,7 +6,7 @@
#include <linux/err.h> #include <linux/err.h>
#include <linux/init.h> #include <linux/init.h>
#include <linux/of_device.h> #include <linux/of.h>
#include <linux/pinctrl/pinctrl.h> #include <linux/pinctrl/pinctrl.h>
#include <linux/platform_device.h> #include <linux/platform_device.h>

2
drivers/pinctrl/freescale/pinctrl-imxrt1170.c
View File

@ -6,7 +6,7 @@
#include <linux/err.h> #include <linux/err.h>
#include <linux/init.h> #include <linux/init.h>
#include <linux/of_device.h> #include <linux/of.h>
#include <linux/pinctrl/pinctrl.h> #include <linux/pinctrl/pinctrl.h>
#include <linux/platform_device.h> #include <linux/platform_device.h>

4
drivers/pinctrl/freescale/pinctrl-vf610.c
View File

@ -7,8 +7,8 @@
#include <linux/err.h> #include <linux/err.h>
#include <linux/init.h> #include <linux/init.h>
#include <linux/io.h> #include <linux/io.h>
#include <linux/of.h> #include <linux/mod_devicetable.h>
#include <linux/of_device.h> #include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h> #include <linux/pinctrl/pinctrl.h>
#include "pinctrl-imx.h" #include "pinctrl-imx.h"

49
drivers/pinctrl/intel/Kconfig
View File

@ -1,11 +1,10 @@
# SPDX-License-Identifier: GPL-2.0 # SPDX-License-Identifier: GPL-2.0
# Intel pin control drivers # Intel pin control drivers
menu "Intel pinctrl drivers" menu "Intel pinctrl drivers"
depends on X86 || COMPILE_TEST depends on ACPI && (X86 || COMPILE_TEST)
config PINCTRL_BAYTRAIL config PINCTRL_BAYTRAIL
bool "Intel Baytrail GPIO pin control" bool "Intel Baytrail GPIO pin control"
depends on ACPI
select PINCTRL_INTEL select PINCTRL_INTEL
help help
driver for memory mapped GPIO functionality on Intel Baytrail driver for memory mapped GPIO functionality on Intel Baytrail
@ -17,7 +16,6 @@ config PINCTRL_BAYTRAIL
config PINCTRL_CHERRYVIEW config PINCTRL_CHERRYVIEW
tristate "Intel Cherryview/Braswell pinctrl and GPIO driver" tristate "Intel Cherryview/Braswell pinctrl and GPIO driver"
depends on ACPI
select PINCTRL_INTEL select PINCTRL_INTEL
help help
Cherryview/Braswell pinctrl driver provides an interface that Cherryview/Braswell pinctrl driver provides an interface that
@ -25,39 +23,12 @@ config PINCTRL_CHERRYVIEW
config PINCTRL_LYNXPOINT config PINCTRL_LYNXPOINT
tristate "Intel Lynxpoint pinctrl and GPIO driver" tristate "Intel Lynxpoint pinctrl and GPIO driver"
depends on ACPI select PINCTRL_INTEL
select PINMUX
select PINCONF
select GENERIC_PINCONF
select GPIOLIB
select GPIOLIB_IRQCHIP
help help
Lynxpoint is the PCH of Intel Haswell. This pinctrl driver Lynxpoint is the PCH of Intel Haswell. This pinctrl driver
provides an interface that allows configuring of PCH pins and provides an interface that allows configuring of PCH pins and
using them as GPIOs. using them as GPIOs.
config PINCTRL_MERRIFIELD
tristate "Intel Merrifield pinctrl driver"
depends on X86_INTEL_MID
select PINMUX
select PINCONF
select GENERIC_PINCONF
help
Merrifield Family-Level Interface Shim (FLIS) driver provides an
interface that allows configuring of SoC pins and using them as
GPIOs.
config PINCTRL_MOOREFIELD
tristate "Intel Moorefield pinctrl driver"
depends on X86_INTEL_MID
select PINMUX
select PINCONF
select GENERIC_PINCONF
help
Moorefield Family-Level Interface Shim (FLIS) driver provides an
interface that allows configuring of SoC pins and using them as
GPIOs.
config PINCTRL_INTEL config PINCTRL_INTEL
tristate tristate
select PINMUX select PINMUX
@ -68,7 +39,6 @@ config PINCTRL_INTEL
config PINCTRL_ALDERLAKE config PINCTRL_ALDERLAKE
tristate "Intel Alder Lake pinctrl and GPIO driver" tristate "Intel Alder Lake pinctrl and GPIO driver"
depends on ACPI
select PINCTRL_INTEL select PINCTRL_INTEL
help help
This pinctrl driver provides an interface that allows configuring This pinctrl driver provides an interface that allows configuring
@ -76,7 +46,6 @@ config PINCTRL_ALDERLAKE
config PINCTRL_BROXTON config PINCTRL_BROXTON
tristate "Intel Broxton pinctrl and GPIO driver" tristate "Intel Broxton pinctrl and GPIO driver"
depends on ACPI
select PINCTRL_INTEL select PINCTRL_INTEL
help help
Broxton pinctrl driver provides an interface that allows Broxton pinctrl driver provides an interface that allows
@ -84,7 +53,6 @@ config PINCTRL_BROXTON
config PINCTRL_CANNONLAKE config PINCTRL_CANNONLAKE
tristate "Intel Cannon Lake PCH pinctrl and GPIO driver" tristate "Intel Cannon Lake PCH pinctrl and GPIO driver"
depends on ACPI
select PINCTRL_INTEL select PINCTRL_INTEL
help help
This pinctrl driver provides an interface that allows configuring This pinctrl driver provides an interface that allows configuring
@ -92,7 +60,6 @@ config PINCTRL_CANNONLAKE
config PINCTRL_CEDARFORK config PINCTRL_CEDARFORK
tristate "Intel Cedar Fork pinctrl and GPIO driver" tristate "Intel Cedar Fork pinctrl and GPIO driver"
depends on ACPI
select PINCTRL_INTEL select PINCTRL_INTEL
help help
This pinctrl driver provides an interface that allows configuring This pinctrl driver provides an interface that allows configuring
@ -100,7 +67,6 @@ config PINCTRL_CEDARFORK
config PINCTRL_DENVERTON config PINCTRL_DENVERTON
tristate "Intel Denverton pinctrl and GPIO driver" tristate "Intel Denverton pinctrl and GPIO driver"
depends on ACPI
select PINCTRL_INTEL select PINCTRL_INTEL
help help
This pinctrl driver provides an interface that allows configuring This pinctrl driver provides an interface that allows configuring
@ -108,7 +74,6 @@ config PINCTRL_DENVERTON
config PINCTRL_ELKHARTLAKE config PINCTRL_ELKHARTLAKE
tristate "Intel Elkhart Lake SoC pinctrl and GPIO driver" tristate "Intel Elkhart Lake SoC pinctrl and GPIO driver"
depends on ACPI
select PINCTRL_INTEL select PINCTRL_INTEL
help help
This pinctrl driver provides an interface that allows configuring This pinctrl driver provides an interface that allows configuring
@ -116,7 +81,6 @@ config PINCTRL_ELKHARTLAKE
config PINCTRL_EMMITSBURG config PINCTRL_EMMITSBURG
tristate "Intel Emmitsburg pinctrl and GPIO driver" tristate "Intel Emmitsburg pinctrl and GPIO driver"
depends on ACPI
select PINCTRL_INTEL select PINCTRL_INTEL
help help
This pinctrl driver provides an interface that allows configuring This pinctrl driver provides an interface that allows configuring
@ -124,7 +88,6 @@ config PINCTRL_EMMITSBURG
config PINCTRL_GEMINILAKE config PINCTRL_GEMINILAKE
tristate "Intel Gemini Lake SoC pinctrl and GPIO driver" tristate "Intel Gemini Lake SoC pinctrl and GPIO driver"
depends on ACPI
select PINCTRL_INTEL select PINCTRL_INTEL
help help
This pinctrl driver provides an interface that allows configuring This pinctrl driver provides an interface that allows configuring
@ -132,7 +95,6 @@ config PINCTRL_GEMINILAKE
config PINCTRL_ICELAKE config PINCTRL_ICELAKE
tristate "Intel Ice Lake PCH pinctrl and GPIO driver" tristate "Intel Ice Lake PCH pinctrl and GPIO driver"
depends on ACPI
select PINCTRL_INTEL select PINCTRL_INTEL
help help
This pinctrl driver provides an interface that allows configuring This pinctrl driver provides an interface that allows configuring
@ -140,7 +102,6 @@ config PINCTRL_ICELAKE
config PINCTRL_JASPERLAKE config PINCTRL_JASPERLAKE
tristate "Intel Jasper Lake PCH pinctrl and GPIO driver" tristate "Intel Jasper Lake PCH pinctrl and GPIO driver"
depends on ACPI
select PINCTRL_INTEL select PINCTRL_INTEL
help help
This pinctrl driver provides an interface that allows configuring This pinctrl driver provides an interface that allows configuring
@ -148,7 +109,6 @@ config PINCTRL_JASPERLAKE
config PINCTRL_LAKEFIELD config PINCTRL_LAKEFIELD
tristate "Intel Lakefield SoC pinctrl and GPIO driver" tristate "Intel Lakefield SoC pinctrl and GPIO driver"
depends on ACPI
select PINCTRL_INTEL select PINCTRL_INTEL
help help
This pinctrl driver provides an interface that allows configuring This pinctrl driver provides an interface that allows configuring
@ -156,7 +116,6 @@ config PINCTRL_LAKEFIELD
config PINCTRL_LEWISBURG config PINCTRL_LEWISBURG
tristate "Intel Lewisburg pinctrl and GPIO driver" tristate "Intel Lewisburg pinctrl and GPIO driver"
depends on ACPI
select PINCTRL_INTEL select PINCTRL_INTEL
help help
This pinctrl driver provides an interface that allows configuring This pinctrl driver provides an interface that allows configuring
@ -164,7 +123,6 @@ config PINCTRL_LEWISBURG
config PINCTRL_METEORLAKE config PINCTRL_METEORLAKE
tristate "Intel Meteor Lake pinctrl and GPIO driver" tristate "Intel Meteor Lake pinctrl and GPIO driver"
depends on ACPI
select PINCTRL_INTEL select PINCTRL_INTEL
help help
This pinctrl driver provides an interface that allows configuring This pinctrl driver provides an interface that allows configuring
@ -172,7 +130,6 @@ config PINCTRL_METEORLAKE
config PINCTRL_SUNRISEPOINT config PINCTRL_SUNRISEPOINT
tristate "Intel Sunrisepoint pinctrl and GPIO driver" tristate "Intel Sunrisepoint pinctrl and GPIO driver"
depends on ACPI
select PINCTRL_INTEL select PINCTRL_INTEL
help help
Sunrisepoint is the PCH of Intel Skylake. This pinctrl driver Sunrisepoint is the PCH of Intel Skylake. This pinctrl driver
@ -181,10 +138,10 @@ config PINCTRL_SUNRISEPOINT
config PINCTRL_TIGERLAKE config PINCTRL_TIGERLAKE
tristate "Intel Tiger Lake pinctrl and GPIO driver" tristate "Intel Tiger Lake pinctrl and GPIO driver"
depends on ACPI
select PINCTRL_INTEL select PINCTRL_INTEL
help help
This pinctrl driver provides an interface that allows configuring This pinctrl driver provides an interface that allows configuring
of Intel Tiger Lake PCH pins and using them as GPIOs. of Intel Tiger Lake PCH pins and using them as GPIOs.
source "drivers/pinctrl/intel/Kconfig.tng"
endmenu endmenu

33
drivers/pinctrl/intel/Kconfig.tng Normal file
View File

@ -0,0 +1,33 @@
# SPDX-License-Identifier: GPL-2.0-only
# Intel Tangier and compatible pin control drivers
if X86_INTEL_MID || COMPILE_TEST
config PINCTRL_TANGIER
tristate
select PINMUX
select PINCONF
select GENERIC_PINCONF
help
This is a library driver for Intel Tangier pin controller and to
be selected and used by respective compatible platform drivers.
If built as a module its name will be pinctrl-tangier.
config PINCTRL_MERRIFIELD
tristate "Intel Merrifield pinctrl driver"
select PINCTRL_TANGIER
help
Intel Merrifield Family-Level Interface Shim (FLIS) driver provides
an interface that allows configuring of SoC pins and using them as
GPIOs.
config PINCTRL_MOOREFIELD
tristate "Intel Moorefield pinctrl driver"
select PINCTRL_TANGIER
help
Intel Moorefield Family-Level Interface Shim (FLIS) driver provides
an interface that allows configuring of SoC pins and using them as
GPIOs.
endif

1
drivers/pinctrl/intel/Makefile
View File

@ -4,6 +4,7 @@
obj-$(CONFIG_PINCTRL_BAYTRAIL) += pinctrl-baytrail.o obj-$(CONFIG_PINCTRL_BAYTRAIL) += pinctrl-baytrail.o
obj-$(CONFIG_PINCTRL_CHERRYVIEW) += pinctrl-cherryview.o obj-$(CONFIG_PINCTRL_CHERRYVIEW) += pinctrl-cherryview.o
obj-$(CONFIG_PINCTRL_LYNXPOINT) += pinctrl-lynxpoint.o obj-$(CONFIG_PINCTRL_LYNXPOINT) += pinctrl-lynxpoint.o
obj-$(CONFIG_PINCTRL_TANGIER) += pinctrl-tangier.o
obj-$(CONFIG_PINCTRL_MERRIFIELD) += pinctrl-merrifield.o obj-$(CONFIG_PINCTRL_MERRIFIELD) += pinctrl-merrifield.o
obj-$(CONFIG_PINCTRL_MOOREFIELD) += pinctrl-moorefield.o obj-$(CONFIG_PINCTRL_MOOREFIELD) += pinctrl-moorefield.o
obj-$(CONFIG_PINCTRL_INTEL) += pinctrl-intel.o obj-$(CONFIG_PINCTRL_INTEL) += pinctrl-intel.o

1
drivers/pinctrl/intel/pinctrl-alderlake.c
View File

@ -748,3 +748,4 @@ module_platform_driver(adl_pinctrl_driver);
MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>"); MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
MODULE_DESCRIPTION("Intel Alder Lake PCH pinctrl/GPIO driver"); MODULE_DESCRIPTION("Intel Alder Lake PCH pinctrl/GPIO driver");
MODULE_LICENSE("GPL v2"); MODULE_LICENSE("GPL v2");
MODULE_IMPORT_NS(PINCTRL_INTEL);

135
drivers/pinctrl/intel/pinctrl-baytrail.c
View File

@ -13,6 +13,7 @@
#include <linux/interrupt.h> #include <linux/interrupt.h>
#include <linux/io.h> #include <linux/io.h>
#include <linux/kernel.h> #include <linux/kernel.h>
#include <linux/module.h>
#include <linux/types.h> #include <linux/types.h>
#include <linux/platform_device.h> #include <linux/platform_device.h>
#include <linux/pm_runtime.h> #include <linux/pm_runtime.h>
@ -551,25 +552,10 @@ static const struct intel_pinctrl_soc_data *byt_soc_data[] = {
static DEFINE_RAW_SPINLOCK(byt_lock); static DEFINE_RAW_SPINLOCK(byt_lock);
static struct intel_community *byt_get_community(struct intel_pinctrl *vg,
unsigned int pin)
{
struct intel_community *comm;
int i;
for (i = 0; i < vg->ncommunities; i++) {
comm = vg->communities + i;
if (pin < comm->pin_base + comm->npins && pin >= comm->pin_base)
return comm;
}
return NULL;
}
static void __iomem *byt_gpio_reg(struct intel_pinctrl *vg, unsigned int offset, static void __iomem *byt_gpio_reg(struct intel_pinctrl *vg, unsigned int offset,
int reg) int reg)
{ {
struct intel_community *comm = byt_get_community(vg, offset); struct intel_community *comm = intel_get_community(vg, offset);
u32 reg_offset; u32 reg_offset;
if (!comm) if (!comm)
@ -591,68 +577,12 @@ static void __iomem *byt_gpio_reg(struct intel_pinctrl *vg, unsigned int offset,
return comm->pad_regs + reg_offset + reg; return comm->pad_regs + reg_offset + reg;
} }
static int byt_get_groups_count(struct pinctrl_dev *pctldev)
{
struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev);
return vg->soc->ngroups;
}
static const char *byt_get_group_name(struct pinctrl_dev *pctldev,
unsigned int selector)
{
struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev);
return vg->soc->groups[selector].grp.name;
}
static int byt_get_group_pins(struct pinctrl_dev *pctldev,
unsigned int selector,
const unsigned int **pins,
unsigned int *num_pins)
{
struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev);
*pins = vg->soc->groups[selector].grp.pins;
*num_pins = vg->soc->groups[selector].grp.npins;
return 0;
}
static const struct pinctrl_ops byt_pinctrl_ops = { static const struct pinctrl_ops byt_pinctrl_ops = {
.get_groups_count = byt_get_groups_count, .get_groups_count = intel_get_groups_count,
.get_group_name = byt_get_group_name, .get_group_name = intel_get_group_name,
.get_group_pins = byt_get_group_pins, .get_group_pins = intel_get_group_pins,
}; };
static int byt_get_functions_count(struct pinctrl_dev *pctldev)
{
struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev);
return vg->soc->nfunctions;
}
static const char *byt_get_function_name(struct pinctrl_dev *pctldev,
unsigned int selector)
{
struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev);
return vg->soc->functions[selector].func.name;
}
static int byt_get_function_groups(struct pinctrl_dev *pctldev,
unsigned int selector,
const char * const **groups,
unsigned int *ngroups)
{
struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev);
*groups = vg->soc->functions[selector].func.groups;
*ngroups = vg->soc->functions[selector].func.ngroups;
return 0;
}
static void byt_set_group_simple_mux(struct intel_pinctrl *vg, static void byt_set_group_simple_mux(struct intel_pinctrl *vg,
const struct intel_pingroup group, const struct intel_pingroup group,
unsigned int func) unsigned int func)
@ -851,9 +781,9 @@ static int byt_gpio_set_direction(struct pinctrl_dev *pctl_dev,
} }
static const struct pinmux_ops byt_pinmux_ops = { static const struct pinmux_ops byt_pinmux_ops = {
.get_functions_count = byt_get_functions_count, .get_functions_count = intel_get_functions_count,
.get_function_name = byt_get_function_name, .get_function_name = intel_get_function_name,
.get_function_groups = byt_get_function_groups, .get_function_groups = intel_get_function_groups,
.set_mux = byt_set_mux, .set_mux = byt_set_mux,
.gpio_request_enable = byt_gpio_request_enable, .gpio_request_enable = byt_gpio_request_enable,
.gpio_disable_free = byt_gpio_disable_free, .gpio_disable_free = byt_gpio_disable_free,
@ -995,8 +925,8 @@ static int byt_pin_config_set(struct pinctrl_dev *pctl_dev,
void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG); void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG); void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
void __iomem *db_reg = byt_gpio_reg(vg, offset, BYT_DEBOUNCE_REG); void __iomem *db_reg = byt_gpio_reg(vg, offset, BYT_DEBOUNCE_REG);
u32 conf, val, db_pulse, debounce;
unsigned long flags; unsigned long flags;
u32 conf, val, debounce;
int i, ret = 0; int i, ret = 0;
raw_spin_lock_irqsave(&byt_lock, flags); raw_spin_lock_irqsave(&byt_lock, flags);
@ -1053,8 +983,6 @@ static int byt_pin_config_set(struct pinctrl_dev *pctl_dev,
break; break;
case PIN_CONFIG_INPUT_DEBOUNCE: case PIN_CONFIG_INPUT_DEBOUNCE:
debounce = readl(db_reg);
if (arg) if (arg)
conf |= BYT_DEBOUNCE_EN; conf |= BYT_DEBOUNCE_EN;
else else
@ -1062,32 +990,25 @@ static int byt_pin_config_set(struct pinctrl_dev *pctl_dev,
switch (arg) { switch (arg) {
case 375: case 375:
debounce &= ~BYT_DEBOUNCE_PULSE_MASK; db_pulse = BYT_DEBOUNCE_PULSE_375US;
debounce |= BYT_DEBOUNCE_PULSE_375US;
break; break;
case 750: case 750:
debounce &= ~BYT_DEBOUNCE_PULSE_MASK; db_pulse = BYT_DEBOUNCE_PULSE_750US;
debounce |= BYT_DEBOUNCE_PULSE_750US;
break; break;
case 1500: case 1500:
debounce &= ~BYT_DEBOUNCE_PULSE_MASK; db_pulse = BYT_DEBOUNCE_PULSE_1500US;
debounce |= BYT_DEBOUNCE_PULSE_1500US;
break; break;
case 3000: case 3000:
debounce &= ~BYT_DEBOUNCE_PULSE_MASK; db_pulse = BYT_DEBOUNCE_PULSE_3MS;
debounce |= BYT_DEBOUNCE_PULSE_3MS;
break; break;
case 6000: case 6000:
debounce &= ~BYT_DEBOUNCE_PULSE_MASK; db_pulse = BYT_DEBOUNCE_PULSE_6MS;
debounce |= BYT_DEBOUNCE_PULSE_6MS;
break; break;
case 12000: case 12000:
debounce &= ~BYT_DEBOUNCE_PULSE_MASK; db_pulse = BYT_DEBOUNCE_PULSE_12MS;
debounce |= BYT_DEBOUNCE_PULSE_12MS;
break; break;
case 24000: case 24000:
debounce &= ~BYT_DEBOUNCE_PULSE_MASK; db_pulse = BYT_DEBOUNCE_PULSE_24MS;
debounce |= BYT_DEBOUNCE_PULSE_24MS;
break; break;
default: default:
if (arg) if (arg)
@ -1095,8 +1016,13 @@ static int byt_pin_config_set(struct pinctrl_dev *pctl_dev,
break; break;
} }
if (!ret) if (ret)
writel(debounce, db_reg); break;
debounce = readl(db_reg);
debounce = (debounce & ~BYT_DEBOUNCE_PULSE_MASK) | db_pulse;
writel(debounce, db_reg);
break; break;
default: default:
ret = -ENOTSUPP; ret = -ENOTSUPP;
@ -1265,7 +1191,7 @@ static void byt_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
val = readl(val_reg); val = readl(val_reg);
raw_spin_unlock_irqrestore(&byt_lock, flags); raw_spin_unlock_irqrestore(&byt_lock, flags);
comm = byt_get_community(vg, pin); comm = intel_get_community(vg, pin);
if (!comm) { if (!comm) {
seq_printf(s, "Pin %i: can't retrieve community\n", pin); seq_printf(s, "Pin %i: can't retrieve community\n", pin);
continue; continue;
@ -1733,7 +1659,6 @@ static int byt_pinctrl_probe(struct platform_device *pdev)
return 0; return 0;
} }
#ifdef CONFIG_PM_SLEEP
static int byt_gpio_suspend(struct device *dev) static int byt_gpio_suspend(struct device *dev)
{ {
struct intel_pinctrl *vg = dev_get_drvdata(dev); struct intel_pinctrl *vg = dev_get_drvdata(dev);
@ -1817,9 +1742,7 @@ static int byt_gpio_resume(struct device *dev)
raw_spin_unlock_irqrestore(&byt_lock, flags); raw_spin_unlock_irqrestore(&byt_lock, flags);
return 0; return 0;
} }
#endif
#ifdef CONFIG_PM
static int byt_gpio_runtime_suspend(struct device *dev) static int byt_gpio_runtime_suspend(struct device *dev)
{ {
return 0; return 0;
@ -1829,19 +1752,17 @@ static int byt_gpio_runtime_resume(struct device *dev)
{ {
return 0; return 0;
} }
#endif
static const struct dev_pm_ops byt_gpio_pm_ops = { static const struct dev_pm_ops byt_gpio_pm_ops = {
SET_LATE_SYSTEM_SLEEP_PM_OPS(byt_gpio_suspend, byt_gpio_resume) LATE_SYSTEM_SLEEP_PM_OPS(byt_gpio_suspend, byt_gpio_resume)
SET_RUNTIME_PM_OPS(byt_gpio_runtime_suspend, byt_gpio_runtime_resume, RUNTIME_PM_OPS(byt_gpio_runtime_suspend, byt_gpio_runtime_resume, NULL)
NULL)
}; };
static struct platform_driver byt_gpio_driver = { static struct platform_driver byt_gpio_driver = {
.probe = byt_pinctrl_probe, .probe = byt_pinctrl_probe,
.driver = { .driver = {
.name = "byt_gpio", .name = "byt_gpio",
.pm = &byt_gpio_pm_ops, .pm = pm_ptr(&byt_gpio_pm_ops),
.acpi_match_table = byt_gpio_acpi_match, .acpi_match_table = byt_gpio_acpi_match,
.suppress_bind_attrs = true, .suppress_bind_attrs = true,
}, },
@ -1852,3 +1773,5 @@ static int __init byt_gpio_init(void)
return platform_driver_register(&byt_gpio_driver); return platform_driver_register(&byt_gpio_driver);
} }
subsys_initcall(byt_gpio_init); subsys_initcall(byt_gpio_init);
MODULE_IMPORT_NS(PINCTRL_INTEL);

1
drivers/pinctrl/intel/pinctrl-broxton.c
View File

@ -1028,3 +1028,4 @@ MODULE_DESCRIPTION("Intel Broxton SoC pinctrl/GPIO driver");
MODULE_LICENSE("GPL v2"); MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:apollolake-pinctrl"); MODULE_ALIAS("platform:apollolake-pinctrl");
MODULE_ALIAS("platform:broxton-pinctrl"); MODULE_ALIAS("platform:broxton-pinctrl");
MODULE_IMPORT_NS(PINCTRL_INTEL);

2
drivers/pinctrl/intel/pinctrl-cannonlake.c
View File

@ -834,9 +834,9 @@ static struct platform_driver cnl_pinctrl_driver = {
.pm = &cnl_pinctrl_pm_ops, .pm = &cnl_pinctrl_pm_ops,
}, },
}; };
module_platform_driver(cnl_pinctrl_driver); module_platform_driver(cnl_pinctrl_driver);
MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>"); MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
MODULE_DESCRIPTION("Intel Cannon Lake PCH pinctrl/GPIO driver"); MODULE_DESCRIPTION("Intel Cannon Lake PCH pinctrl/GPIO driver");
MODULE_LICENSE("GPL v2"); MODULE_LICENSE("GPL v2");
MODULE_IMPORT_NS(PINCTRL_INTEL);

1
drivers/pinctrl/intel/pinctrl-cedarfork.c
View File

@ -351,3 +351,4 @@ module_exit(cdf_pinctrl_exit);
MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>"); MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
MODULE_DESCRIPTION("Intel Cedar Fork PCH pinctrl/GPIO driver"); MODULE_DESCRIPTION("Intel Cedar Fork PCH pinctrl/GPIO driver");
MODULE_LICENSE("GPL v2"); MODULE_LICENSE("GPL v2");
MODULE_IMPORT_NS(PINCTRL_INTEL);

84
drivers/pinctrl/intel/pinctrl-cherryview.c
View File

@ -617,31 +617,6 @@ static bool chv_pad_locked(struct intel_pinctrl *pctrl, unsigned int offset)
return chv_readl(pctrl, offset, CHV_PADCTRL1) & CHV_PADCTRL1_CFGLOCK; return chv_readl(pctrl, offset, CHV_PADCTRL1) & CHV_PADCTRL1_CFGLOCK;
} }
static int chv_get_groups_count(struct pinctrl_dev *pctldev)
{
struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
return pctrl->soc->ngroups;
}
static const char *chv_get_group_name(struct pinctrl_dev *pctldev,
unsigned int group)
{
struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
return pctrl->soc->groups[group].grp.name;
}
static int chv_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group,
const unsigned int **pins, unsigned int *npins)
{
struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
*pins = pctrl->soc->groups[group].grp.pins;
*npins = pctrl->soc->groups[group].grp.npins;
return 0;
}
static void chv_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, static void chv_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
unsigned int offset) unsigned int offset)
{ {
@ -676,39 +651,12 @@ static void chv_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
} }
static const struct pinctrl_ops chv_pinctrl_ops = { static const struct pinctrl_ops chv_pinctrl_ops = {
.get_groups_count = chv_get_groups_count, .get_groups_count = intel_get_groups_count,
.get_group_name = chv_get_group_name, .get_group_name = intel_get_group_name,
.get_group_pins = chv_get_group_pins, .get_group_pins = intel_get_group_pins,
.pin_dbg_show = chv_pin_dbg_show, .pin_dbg_show = chv_pin_dbg_show,
}; };
static int chv_get_functions_count(struct pinctrl_dev *pctldev)
{
struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
return pctrl->soc->nfunctions;
}
static const char *chv_get_function_name(struct pinctrl_dev *pctldev,
unsigned int function)
{
struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
return pctrl->soc->functions[function].func.name;
}
static int chv_get_function_groups(struct pinctrl_dev *pctldev,
unsigned int function,
const char * const **groups,
unsigned int * const ngroups)
{
struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
*groups = pctrl->soc->functions[function].func.groups;
*ngroups = pctrl->soc->functions[function].func.ngroups;
return 0;
}
static int chv_pinmux_set_mux(struct pinctrl_dev *pctldev, static int chv_pinmux_set_mux(struct pinctrl_dev *pctldev,
unsigned int function, unsigned int group) unsigned int function, unsigned int group)
{ {
@ -884,9 +832,9 @@ static int chv_gpio_set_direction(struct pinctrl_dev *pctldev,
} }
static const struct pinmux_ops chv_pinmux_ops = { static const struct pinmux_ops chv_pinmux_ops = {
.get_functions_count = chv_get_functions_count, .get_functions_count = intel_get_functions_count,
.get_function_name = chv_get_function_name, .get_function_name = intel_get_function_name,
.get_function_groups = chv_get_function_groups, .get_function_groups = intel_get_function_groups,
.set_mux = chv_pinmux_set_mux, .set_mux = chv_pinmux_set_mux,
.gpio_request_enable = chv_gpio_request_enable, .gpio_request_enable = chv_gpio_request_enable,
.gpio_disable_free = chv_gpio_disable_free, .gpio_disable_free = chv_gpio_disable_free,
@ -1118,7 +1066,7 @@ static int chv_config_group_get(struct pinctrl_dev *pctldev,
unsigned int npins; unsigned int npins;
int ret; int ret;
ret = chv_get_group_pins(pctldev, group, &pins, &npins); ret = intel_get_group_pins(pctldev, group, &pins, &npins);
if (ret) if (ret)
return ret; return ret;
@ -1137,7 +1085,7 @@ static int chv_config_group_set(struct pinctrl_dev *pctldev,
unsigned int npins; unsigned int npins;
int i, ret; int i, ret;
ret = chv_get_group_pins(pctldev, group, &pins, &npins); ret = intel_get_group_pins(pctldev, group, &pins, &npins);
if (ret) if (ret)
return ret; return ret;
@ -1701,7 +1649,6 @@ static int chv_pinctrl_probe(struct platform_device *pdev)
struct intel_community_context *cctx; struct intel_community_context *cctx;
struct intel_community *community; struct intel_community *community;
struct device *dev = &pdev->dev; struct device *dev = &pdev->dev;
struct acpi_device *adev = ACPI_COMPANION(dev);
struct intel_pinctrl *pctrl; struct intel_pinctrl *pctrl;
acpi_status status; acpi_status status;
unsigned int i; unsigned int i;
@ -1769,7 +1716,7 @@ static int chv_pinctrl_probe(struct platform_device *pdev)
if (ret) if (ret)
return ret; return ret;
status = acpi_install_address_space_handler(adev->handle, status = acpi_install_address_space_handler(ACPI_HANDLE(dev),
community->acpi_space_id, community->acpi_space_id,
chv_pinctrl_mmio_access_handler, chv_pinctrl_mmio_access_handler,
NULL, pctrl); NULL, pctrl);
@ -1786,14 +1733,13 @@ static int chv_pinctrl_remove(struct platform_device *pdev)
struct intel_pinctrl *pctrl = platform_get_drvdata(pdev); struct intel_pinctrl *pctrl = platform_get_drvdata(pdev);
const struct intel_community *community = &pctrl->communities[0]; const struct intel_community *community = &pctrl->communities[0];
acpi_remove_address_space_handler(ACPI_COMPANION(&pdev->dev), acpi_remove_address_space_handler(ACPI_HANDLE(&pdev->dev),
community->acpi_space_id, community->acpi_space_id,
chv_pinctrl_mmio_access_handler); chv_pinctrl_mmio_access_handler);
return 0; return 0;
} }
#ifdef CONFIG_PM_SLEEP
static int chv_pinctrl_suspend_noirq(struct device *dev) static int chv_pinctrl_suspend_noirq(struct device *dev)
{ {
struct intel_pinctrl *pctrl = dev_get_drvdata(dev); struct intel_pinctrl *pctrl = dev_get_drvdata(dev);
@ -1877,12 +1823,9 @@ static int chv_pinctrl_resume_noirq(struct device *dev)
return 0; return 0;
} }
#endif
static const struct dev_pm_ops chv_pinctrl_pm_ops = { static DEFINE_NOIRQ_DEV_PM_OPS(chv_pinctrl_pm_ops,
SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(chv_pinctrl_suspend_noirq, chv_pinctrl_suspend_noirq, chv_pinctrl_resume_noirq);
chv_pinctrl_resume_noirq)
};
static const struct acpi_device_id chv_pinctrl_acpi_match[] = { static const struct acpi_device_id chv_pinctrl_acpi_match[] = {
{ "INT33FF", (kernel_ulong_t)chv_soc_data }, { "INT33FF", (kernel_ulong_t)chv_soc_data },
@ -1895,7 +1838,7 @@ static struct platform_driver chv_pinctrl_driver = {
.remove = chv_pinctrl_remove, .remove = chv_pinctrl_remove,
.driver = { .driver = {
.name = "cherryview-pinctrl", .name = "cherryview-pinctrl",
.pm = &chv_pinctrl_pm_ops, .pm = pm_sleep_ptr(&chv_pinctrl_pm_ops),
.acpi_match_table = chv_pinctrl_acpi_match, .acpi_match_table = chv_pinctrl_acpi_match,
}, },
}; };
@ -1915,3 +1858,4 @@ module_exit(chv_pinctrl_exit);
MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>"); MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
MODULE_DESCRIPTION("Intel Cherryview/Braswell pinctrl driver"); MODULE_DESCRIPTION("Intel Cherryview/Braswell pinctrl driver");
MODULE_LICENSE("GPL v2"); MODULE_LICENSE("GPL v2");
MODULE_IMPORT_NS(PINCTRL_INTEL);

1
drivers/pinctrl/intel/pinctrl-denverton.c
View File

@ -281,3 +281,4 @@ module_exit(dnv_pinctrl_exit);
MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>"); MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
MODULE_DESCRIPTION("Intel Denverton SoC pinctrl/GPIO driver"); MODULE_DESCRIPTION("Intel Denverton SoC pinctrl/GPIO driver");
MODULE_LICENSE("GPL v2"); MODULE_LICENSE("GPL v2");
MODULE_IMPORT_NS(PINCTRL_INTEL);

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