mt76: mt7615: add Smart Carrier Sense support
Introduce Smart Carrier Sense support in order to tune device sensitivity according to RTS error rate and False CCA reported by the radio Tested-by: Ryder Lee <ryder.lee@mediatek.com> Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org> Signed-off-by: Felix Fietkau <nbd@nbd.name>
This commit is contained in:
Lorenzo Bianconi
Felix Fietkau
parent
7fe9654152
commit
49de79ad9a
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@ -13,6 +13,42 @@ mt7615_radar_pattern_set(void *data, u64 val)
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DEFINE_DEBUGFS_ATTRIBUTE(fops_radar_pattern, NULL,
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mt7615_radar_pattern_set, "%lld\n");
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static int
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mt7615_scs_set(void *data, u64 val)
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{
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struct mt7615_dev *dev = data;
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mt7615_mac_set_scs(dev, val);
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return 0;
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}
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static int
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mt7615_scs_get(void *data, u64 *val)
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{
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struct mt7615_dev *dev = data;
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*val = dev->scs_en;
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return 0;
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}
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DEFINE_DEBUGFS_ATTRIBUTE(fops_scs, mt7615_scs_get,
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mt7615_scs_set, "%lld\n");
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static int
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mt7615_radio_read(struct seq_file *s, void *data)
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{
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struct mt7615_dev *dev = dev_get_drvdata(s->private);
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seq_printf(s, "Sensitivity: ofdm=%d cck=%d\n",
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dev->ofdm_sensitivity, dev->cck_sensitivity);
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seq_printf(s, "False CCA: ofdm=%d cck=%d\n",
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dev->false_cca_ofdm, dev->false_cca_cck);
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return 0;
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}
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int mt7615_init_debugfs(struct mt7615_dev *dev)
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{
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struct dentry *dir;
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@ -21,6 +57,9 @@ int mt7615_init_debugfs(struct mt7615_dev *dev)
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if (!dir)
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return -ENOMEM;
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debugfs_create_file("scs", 0600, dir, dev, &fops_scs);
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debugfs_create_devm_seqfile(dev->mt76.dev, "radio", dir,
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mt7615_radio_read);
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debugfs_create_u32("dfs_hw_pattern", 0400, dir, &dev->hw_pattern);
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/* test pattern knobs */
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debugfs_create_u8("pattern_len", 0600, dir,
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@ -50,6 +50,7 @@ static void mt7615_mac_init(struct mt7615_dev *dev)
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MT_TMAC_CTCR0_INS_DDLMT_EN);
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mt7615_mcu_set_rts_thresh(dev, 0x92b);
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mt7615_mac_set_scs(dev, false);
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mt76_rmw(dev, MT_AGG_SCR, MT_AGG_SCR_NLNAV_MID_PTEC_DIS,
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MT_AGG_SCR_NLNAV_MID_PTEC_DIS);
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@ -986,6 +986,175 @@ void mt7615_mac_tx_free(struct mt7615_dev *dev, struct sk_buff *skb)
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dev_kfree_skb(skb);
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}
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static void
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mt7615_mac_set_default_sensitivity(struct mt7615_dev *dev)
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{
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mt76_rmw(dev, MT_WF_PHY_B0_MIN_PRI_PWR,
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MT_WF_PHY_B0_PD_OFDM_MASK,
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MT_WF_PHY_B0_PD_OFDM(0x13c));
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mt76_rmw(dev, MT_WF_PHY_B1_MIN_PRI_PWR,
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MT_WF_PHY_B1_PD_OFDM_MASK,
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MT_WF_PHY_B1_PD_OFDM(0x13c));
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mt76_rmw(dev, MT_WF_PHY_B0_RXTD_CCK_PD,
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MT_WF_PHY_B0_PD_CCK_MASK,
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MT_WF_PHY_B0_PD_CCK(0x92));
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mt76_rmw(dev, MT_WF_PHY_B1_RXTD_CCK_PD,
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MT_WF_PHY_B1_PD_CCK_MASK,
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MT_WF_PHY_B1_PD_CCK(0x92));
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dev->ofdm_sensitivity = -98;
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dev->cck_sensitivity = -110;
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dev->last_cca_adj = jiffies;
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}
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void mt7615_mac_set_scs(struct mt7615_dev *dev, bool enable)
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{
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mutex_lock(&dev->mt76.mutex);
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if (dev->scs_en == enable)
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goto out;
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if (enable) {
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/* DBDC not supported */
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mt76_set(dev, MT_WF_PHY_B0_MIN_PRI_PWR,
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MT_WF_PHY_B0_PD_BLK);
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if (is_mt7622(&dev->mt76)) {
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mt76_set(dev, MT_MIB_M0_MISC_CR, 0x7 << 8);
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mt76_set(dev, MT_MIB_M0_MISC_CR, 0x7);
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}
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} else {
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mt76_clear(dev, MT_WF_PHY_B0_MIN_PRI_PWR,
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MT_WF_PHY_B0_PD_BLK);
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mt76_clear(dev, MT_WF_PHY_B1_MIN_PRI_PWR,
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MT_WF_PHY_B1_PD_BLK);
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}
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mt7615_mac_set_default_sensitivity(dev);
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dev->scs_en = enable;
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out:
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mutex_unlock(&dev->mt76.mutex);
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}
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void mt7615_mac_cca_stats_reset(struct mt7615_dev *dev)
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{
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mt76_clear(dev, MT_WF_PHY_R0_B0_PHYMUX_5, GENMASK(22, 20));
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mt76_set(dev, MT_WF_PHY_R0_B0_PHYMUX_5, BIT(22) | BIT(20));
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}
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static void
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mt7615_mac_adjust_sensitivity(struct mt7615_dev *dev,
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u32 rts_err_rate, bool ofdm)
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{
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int false_cca = ofdm ? dev->false_cca_ofdm : dev->false_cca_cck;
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u16 def_th = ofdm ? -98 : -110;
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bool update = false;
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s8 *sensitivity;
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int signal;
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sensitivity = ofdm ? &dev->ofdm_sensitivity : &dev->cck_sensitivity;
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signal = mt76_get_min_avg_rssi(&dev->mt76);
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if (!signal) {
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mt7615_mac_set_default_sensitivity(dev);
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return;
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}
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signal = min(signal, -72);
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if (false_cca > 500) {
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if (rts_err_rate > MT_FRAC(40, 100))
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return;
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/* decrease coverage */
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if (*sensitivity == def_th && signal > -90) {
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*sensitivity = -90;
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update = true;
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} else if (*sensitivity + 2 < signal) {
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*sensitivity += 2;
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update = true;
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}
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} else if ((false_cca > 0 && false_cca < 50) ||
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rts_err_rate > MT_FRAC(60, 100)) {
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/* increase coverage */
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if (*sensitivity - 2 >= def_th) {
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*sensitivity -= 2;
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update = true;
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}
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}
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if (*sensitivity > signal) {
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*sensitivity = signal;
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update = true;
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}
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if (update) {
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u16 val;
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if (ofdm) {
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/* DBDC not supported */
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val = *sensitivity * 2 + 512;
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mt76_rmw(dev, MT_WF_PHY_B0_MIN_PRI_PWR,
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MT_WF_PHY_B0_PD_OFDM_MASK,
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MT_WF_PHY_B0_PD_OFDM(val));
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} else {
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val = *sensitivity + 256;
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mt76_rmw(dev, MT_WF_PHY_B0_RXTD_CCK_PD,
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MT_WF_PHY_B0_PD_CCK_MASK,
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MT_WF_PHY_B0_PD_CCK(val));
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mt76_rmw(dev, MT_WF_PHY_B1_RXTD_CCK_PD,
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MT_WF_PHY_B1_PD_CCK_MASK,
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MT_WF_PHY_B1_PD_CCK(val));
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}
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dev->last_cca_adj = jiffies;
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}
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}
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static void
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mt7615_mac_scs_check(struct mt7615_dev *dev)
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{
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u32 val, rts_cnt = 0, rts_retries_cnt = 0, rts_err_rate = 0;
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u32 mdrdy_cck, mdrdy_ofdm, pd_cck, pd_ofdm;
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int i;
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if (!dev->scs_en)
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return;
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for (i = 0; i < 4; i++) {
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u32 data;
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val = mt76_rr(dev, MT_MIB_MB_SDR0(i));
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data = FIELD_GET(MT_MIB_RTS_RETRIES_COUNT_MASK, val);
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if (data > rts_retries_cnt) {
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rts_cnt = FIELD_GET(MT_MIB_RTS_COUNT_MASK, val);
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rts_retries_cnt = data;
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}
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}
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val = mt76_rr(dev, MT_WF_PHY_R0_B0_PHYCTRL_STS0);
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pd_cck = FIELD_GET(MT_WF_PHYCTRL_STAT_PD_CCK, val);
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pd_ofdm = FIELD_GET(MT_WF_PHYCTRL_STAT_PD_OFDM, val);
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val = mt76_rr(dev, MT_WF_PHY_R0_B0_PHYCTRL_STS5);
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mdrdy_cck = FIELD_GET(MT_WF_PHYCTRL_STAT_MDRDY_CCK, val);
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mdrdy_ofdm = FIELD_GET(MT_WF_PHYCTRL_STAT_MDRDY_OFDM, val);
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dev->false_cca_ofdm = pd_ofdm - mdrdy_ofdm;
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dev->false_cca_cck = pd_cck - mdrdy_cck;
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mt7615_mac_cca_stats_reset(dev);
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if (rts_cnt + rts_retries_cnt)
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rts_err_rate = MT_FRAC(rts_retries_cnt,
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rts_cnt + rts_retries_cnt);
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/* cck */
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mt7615_mac_adjust_sensitivity(dev, rts_err_rate, false);
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/* ofdm */
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mt7615_mac_adjust_sensitivity(dev, rts_err_rate, true);
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if (time_after(jiffies, dev->last_cca_adj + 10 * HZ))
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mt7615_mac_set_default_sensitivity(dev);
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}
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void mt7615_mac_work(struct work_struct *work)
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{
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struct mt7615_dev *dev;
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@ -993,6 +1162,13 @@ void mt7615_mac_work(struct work_struct *work)
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dev = (struct mt7615_dev *)container_of(work, struct mt76_dev,
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mac_work.work);
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mutex_lock(&dev->mt76.mutex);
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if (++dev->mac_work_count == 5) {
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mt7615_mac_scs_check(dev);
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dev->mac_work_count = 0;
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}
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mutex_unlock(&dev->mt76.mutex);
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mt76_tx_status_check(&dev->mt76, NULL, false);
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ieee80211_queue_delayed_work(mt76_hw(dev), &dev->mt76.mac_work,
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MT7615_WATCHDOG_TIME);
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@ -148,6 +148,7 @@ static int mt7615_set_channel(struct mt7615_dev *dev)
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goto out;
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ret = mt7615_dfs_init_radar_detector(dev);
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mt7615_mac_cca_stats_reset(dev);
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out:
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clear_bit(MT76_RESET, &dev->mt76.state);
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@ -33,6 +33,9 @@
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#define MT7615_EEPROM_SIZE 1024
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#define MT7615_TOKEN_SIZE 4096
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#define MT_FRAC_SCALE 12
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#define MT_FRAC(val, div) (((val) << MT_FRAC_SCALE) / (div))
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struct mt7615_vif;
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struct mt7615_sta;
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@ -87,6 +90,13 @@ struct mt7615_dev {
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u32 hw_pattern;
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int dfs_state;
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int false_cca_ofdm, false_cca_cck;
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unsigned long last_cca_adj;
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u8 mac_work_count;
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s8 ofdm_sensitivity;
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s8 cck_sensitivity;
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bool scs_en;
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spinlock_t token_lock;
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struct idr token;
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};
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@ -192,6 +202,11 @@ int mt7615_dfs_start_radar_detector(struct mt7615_dev *dev);
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int mt7615_dfs_stop_radar_detector(struct mt7615_dev *dev);
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int mt7615_mcu_rdd_send_pattern(struct mt7615_dev *dev);
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static inline bool is_mt7622(struct mt76_dev *dev)
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{
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return mt76_chip(dev) == 0x7622;
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}
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static inline void mt7615_dfs_check_channel(struct mt7615_dev *dev)
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{
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enum nl80211_chan_width width = dev->mt76.chandef.width;
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@ -213,6 +228,8 @@ static inline void mt7615_irq_disable(struct mt7615_dev *dev, u32 mask)
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mt76_set_irq_mask(&dev->mt76, MT_INT_MASK_CSR, mask, 0);
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}
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void mt7615_mac_cca_stats_reset(struct mt7615_dev *dev);
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void mt7615_mac_set_scs(struct mt7615_dev *dev, bool enable);
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int mt7615_mac_write_txwi(struct mt7615_dev *dev, __le32 *txwi,
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struct sk_buff *skb, struct mt76_wcid *wcid,
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struct ieee80211_sta *sta, int pid,
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@ -71,6 +71,34 @@
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#define MT_WF_PHY_WF2_RFCTRL0 MT_WF_PHY(0x1900)
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#define MT_WF_PHY_WF2_RFCTRL0_LPBCN_EN BIT(9)
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#define MT_WF_PHY_R0_B0_PHYMUX_5 MT_WF_PHY(0x0614)
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#define MT_WF_PHY_R0_B0_PHYCTRL_STS0 MT_WF_PHY(0x020c)
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#define MT_WF_PHYCTRL_STAT_PD_OFDM GENMASK(31, 16)
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#define MT_WF_PHYCTRL_STAT_PD_CCK GENMASK(15, 0)
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#define MT_WF_PHY_R0_B0_PHYCTRL_STS5 MT_WF_PHY(0x0220)
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#define MT_WF_PHYCTRL_STAT_MDRDY_OFDM GENMASK(31, 16)
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#define MT_WF_PHYCTRL_STAT_MDRDY_CCK GENMASK(15, 0)
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#define MT_WF_PHY_B0_MIN_PRI_PWR MT_WF_PHY(0x229c)
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#define MT_WF_PHY_B0_PD_OFDM_MASK GENMASK(28, 20)
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#define MT_WF_PHY_B0_PD_OFDM(v) ((v) << 20)
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#define MT_WF_PHY_B0_PD_BLK BIT(19)
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#define MT_WF_PHY_B1_MIN_PRI_PWR MT_WF_PHY(0x084)
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#define MT_WF_PHY_B1_PD_OFDM_MASK GENMASK(24, 16)
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#define MT_WF_PHY_B1_PD_OFDM(v) ((v) << 16)
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#define MT_WF_PHY_B1_PD_BLK BIT(25)
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#define MT_WF_PHY_B0_RXTD_CCK_PD MT_WF_PHY(0x2310)
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#define MT_WF_PHY_B0_PD_CCK_MASK GENMASK(8, 1)
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#define MT_WF_PHY_B0_PD_CCK(v) ((v) << 1)
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#define MT_WF_PHY_B1_RXTD_CCK_PD MT_WF_PHY(0x2314)
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#define MT_WF_PHY_B1_PD_CCK_MASK GENMASK(31, 24)
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#define MT_WF_PHY_B1_PD_CCK(v) ((v) << 24)
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#define MT_WF_CFG_BASE 0x20200
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#define MT_WF_CFG(ofs) (MT_WF_CFG_BASE + (ofs))
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@ -219,6 +247,14 @@
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#define MT_LPON_UTTR0 MT_LPON(0x018)
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#define MT_LPON_UTTR1 MT_LPON(0x01c)
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#define MT_WF_MIB_BASE 0x24800
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#define MT_WF_MIB(ofs) (MT_WF_MIB_BASE + (ofs))
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#define MT_MIB_M0_MISC_CR MT_WF_MIB(0x00c)
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#define MT_MIB_MB_SDR0(n) MT_WF_MIB(0x100 + ((n) << 4))
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#define MT_MIB_RTS_RETRIES_COUNT_MASK GENMASK(31, 16)
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#define MT_MIB_RTS_COUNT_MASK GENMASK(15, 0)
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#define MT_EFUSE_BASE 0x81070000
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#define MT_EFUSE_BASE_CTRL 0x000
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#define MT_EFUSE_BASE_CTRL_EMPTY BIT(30)
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