Add Phytium ADC support
Phytium Pe220x SoCs includes an 8-channel, 10-bit single ended ADC
This patch add this ADC driver support
Signed-off-by: wangzhimin <wangzhimin1179@phytium.com.cn>
(cherry picked from commit 0b1dadff13)
Signed-off-by: Alex Shi <alexsshi@tencent.com>
This commit is contained in:
wangzhimin
Jianping Liu
parent
ff857f9fcf
commit
49de6b0c5f
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@ -1096,4 +1096,16 @@ config XILINX_XADC
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The driver can also be build as a module. If so, the module will be called
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xilinx-xadc.
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config PHYTIUM_ADC
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tristate "Phytium ADC driver"
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depends on ARCH_PHYTIUM || COMPILE_TEST
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select IIO_BUFFER
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select IIO_TRIGGERED_BUFFER
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help
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Say yes here to build support for Phytium analog to digital
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converters (ADC).
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To compile this driver as a module, choose M here: the module
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will be called phytium-adc.
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endmenu
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@ -100,3 +100,4 @@ obj-$(CONFIG_VIPERBOARD_ADC) += viperboard_adc.o
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xilinx-xadc-y := xilinx-xadc-core.o xilinx-xadc-events.o
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obj-$(CONFIG_XILINX_XADC) += xilinx-xadc.o
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obj-$(CONFIG_SD_ADC_MODULATOR) += sd_adc_modulator.o
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obj-$(CONFIG_PHYTIUM_ADC) += phytium-adc.o
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@ -0,0 +1,689 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Phytium ADC device driver
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*
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* Copyright (C) 2021-2023, Phytium Technology Co., Ltd.
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*/
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#include <linux/clk.h>
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#include <linux/completion.h>
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#include <linux/err.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/of_device.h>
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#include <linux/iio/iio.h>
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#include <linux/iio/events.h>
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#include <linux/iio/buffer.h>
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#include <linux/iio/trigger.h>
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#include <linux/iio/triggered_buffer.h>
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#include <linux/iio/trigger_consumer.h>
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#include <linux/iio/sysfs.h>
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/* ADC register */
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#define ADC_CTRL_REG 0x00
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#define ADC_CTRL_REG_PD_EN BIT(31)
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#define ADC_CTRL_REG_CH_ONLY_S(x) ((x & 0x7) << 16)
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#define ADC_CTRL_REG_CLK_DIV(x) ((x) << 12)
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#define ADC_CTRL_REG_CHANNEL_EN(x) BIT((x) + 4)
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#define ADC_CTRL_REG_CH_ONLY_EN BIT(3)
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#define ADC_CTRL_REG_SINGLE_EN BIT(2)
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#define ADC_CTRL_REG_SINGLE_SEL BIT(1)
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#define ADC_CTRL_REG_SOC_EN BIT(0)
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#define ADC_INTER_REG 0x04
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#define ADC_STATE_REG 0x08
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#define ADC_STATE_REG_B_STA(x) ((x) << 8)
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#define ADC_STATE_REG_EOC_STA BIT(7)
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#define ADC_STATE_REG_S_STA(x) ((x) << 4)
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#define ADC_STATE_REG_SOC_STA BIT(3)
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#define ADC_STATE_REG_ERR_STA BIT(2)
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#define ADC_STATE_REG_COV_FINISH_STA BIT(1)
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#define ADC_STATE_REG_ADCCTL_BUSY_STA BIT(0)
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#define ADC_ERRCLR_REG 0x0c
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#define ADC_LEVEL_REG(x) (0x10 + ((x) << 2))
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#define ADC_LEVEL_REG_HIGH_LEVEL(x) ((x) << 16)
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#define ADC_LEVEL_REG_LOW_LEVEL(x) (x)
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#define ADC_INTRMASK_REG 0x30
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#define ADC_INTRMASK_REG_ERR_INTR_MASK BIT(24)
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#define ADC_INTRMASK_REG_ULIMIT_OFF(x) BIT(9 + ((x) << 1))
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#define ADC_INTRMASK_REG_DLIMIT_MASK(x) BIT(8 + ((x) << 1))
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#define ADC_INTRMASK_REG_COVFIN_MASK(x) BIT((x))
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#define ADC_INTR_REG 0x34
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#define ADC_INTR_REG_ERR BIT(24)
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#define ADC_INTR_REG_ULIMIT(x) BIT(9 + ((x) << 1))
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#define ADC_INTR_REG_DLIMIT(x) BIT(8 + ((x) << 1))
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#define ADC_INTR_REG_LIMIT_MASK GENMASK(23, 8)
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#define ADC_INTR_REG_COVFIN(x) BIT((x))
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#define ADC_INTR_REG_COVFIN_MASK GENMASK(7, 0)
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#define ADC_COV_RESULT_REG(x) (0x38 + ((x) << 2))
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#define ADC_COV_RESULT_REG_MASK GENMASK(9, 0)
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#define ADC_FINISH_CNT_REG(x) (0x58 + ((x) << 2))
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#define ADC_HIS_LIMIT_REG(x) (0x78 + ((x) << 2))
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#define PHYTIUM_MAX_CHANNELS 8
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#define PHYTIUM_ADC_TIMEOUT usecs_to_jiffies(1000 * 1000)
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static const struct iio_event_spec phytium_adc_event[] = {
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{
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.type = IIO_EV_TYPE_THRESH,
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.dir = IIO_EV_DIR_RISING,
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.mask_separate = BIT(IIO_EV_INFO_VALUE),
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}, {
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.type = IIO_EV_TYPE_THRESH,
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.dir = IIO_EV_DIR_FALLING,
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.mask_separate = BIT(IIO_EV_INFO_VALUE),
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},
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};
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struct phytium_adc_data {
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const struct iio_chan_spec *channels;
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u8 num_channels;
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};
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struct phytium_adc {
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struct device *dev;
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void __iomem *regs;
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struct clk *adc_clk;
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u32 interval;
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u16 thresh_high[PHYTIUM_MAX_CHANNELS];
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u16 thresh_low[PHYTIUM_MAX_CHANNELS];
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u16 last_val[PHYTIUM_MAX_CHANNELS];
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const struct phytium_adc_data *data;
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u16 *scan_data;
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struct completion completion;
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struct mutex lock;
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};
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static ssize_t phytium_adc_show_conv_interval(struct iio_dev *indio_dev,
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uintptr_t priv,
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struct iio_chan_spec const *ch,
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char *buf)
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{
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struct phytium_adc *adc = iio_priv(indio_dev);
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return sprintf(buf, "%u\n", adc->interval);
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}
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static ssize_t phytium_adc_store_conv_interval(struct iio_dev *indio_dev,
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uintptr_t priv,
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struct iio_chan_spec const *ch,
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const char *buf, size_t len)
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{
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struct phytium_adc *adc = iio_priv(indio_dev);
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u32 interval;
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int ret;
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ret = kstrtou32(buf, 0, &interval);
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if (ret < 0)
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return ret;
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mutex_lock(&adc->lock);
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adc->interval = interval;
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mutex_unlock(&adc->lock);
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return len;
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}
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static const struct iio_chan_spec_ext_info phytium_adc_ext_info[] = {
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{
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.name = "conv_interval",
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.read = phytium_adc_show_conv_interval,
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.write = phytium_adc_store_conv_interval,
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},
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{ /* sentinel */ }
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};
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static int phytium_adc_parse_properties(struct platform_device *pdev, struct phytium_adc *adc)
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{
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struct iio_chan_spec *chan_array;
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struct fwnode_handle *fwnode;
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struct phytium_adc_data *data;
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unsigned int channel;
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int num_channels;
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int ret, i = 0;
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data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
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if (!data)
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return -ENOMEM;
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num_channels = device_get_child_node_count(&pdev->dev);
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if (!num_channels) {
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dev_err(&pdev->dev, "no channel children\n");
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return -ENODEV;
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}
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if (num_channels > PHYTIUM_MAX_CHANNELS) {
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dev_err(&pdev->dev, "num of channel children out of range\n");
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return -EINVAL;
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}
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chan_array = devm_kcalloc(&pdev->dev, num_channels, sizeof(*chan_array),
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GFP_KERNEL);
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if (!chan_array)
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return -ENOMEM;
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device_for_each_child_node(&pdev->dev, fwnode) {
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ret = fwnode_property_read_u32(fwnode, "reg", &channel);
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if (ret)
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return ret;
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if (channel >= PHYTIUM_MAX_CHANNELS)
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return -EINVAL;
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chan_array[i].type = IIO_VOLTAGE;
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chan_array[i].indexed = 1;
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chan_array[i].channel = channel;
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chan_array[i].info_mask_separate = BIT(IIO_CHAN_INFO_RAW);
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chan_array[i].event_spec = phytium_adc_event;
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chan_array[i].num_event_specs = ARRAY_SIZE(phytium_adc_event);
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chan_array[i].scan_index = channel;
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chan_array[i].scan_type.sign = 'u';
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chan_array[i].scan_type.realbits = 10;
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chan_array[i].scan_type.storagebits = 16;
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chan_array[i].scan_type.endianness = IIO_LE;
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chan_array[i].ext_info = phytium_adc_ext_info;
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i++;
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}
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data->num_channels = num_channels;
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data->channels = chan_array;
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adc->data = data;
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return 0;
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}
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static void phytium_adc_start_stop(struct phytium_adc *adc, bool start)
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{
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u32 ctrl;
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ctrl = readl(adc->regs + ADC_CTRL_REG);
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if (start)
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ctrl |= ADC_CTRL_REG_SOC_EN | ADC_CTRL_REG_SINGLE_EN;
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else
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ctrl &= ~ADC_CTRL_REG_SOC_EN;
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/* Start conversion */
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writel(ctrl, adc->regs + ADC_CTRL_REG);
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}
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static void phytium_adc_power_setup(struct phytium_adc *adc, bool on)
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{
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u32 reg;
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reg = readl(adc->regs + ADC_CTRL_REG);
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if (on)
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reg &= ~ADC_CTRL_REG_PD_EN;
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else
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reg |= ADC_CTRL_REG_PD_EN;
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writel(reg, adc->regs + ADC_CTRL_REG);
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}
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static int phytium_adc_hw_init(struct phytium_adc *adc)
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{
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int ret;
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u32 reg;
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ret = clk_prepare_enable(adc->adc_clk);
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if (ret)
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return ret;
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/*
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* Setup ctrl register:
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* - Power up conversion module
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* - Set the division by 4 as default
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*/
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reg = ADC_CTRL_REG_CLK_DIV(4);
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writel(reg, adc->regs + ADC_CTRL_REG);
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/* Set all the interrupt mask, unmask them when necessary. */
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writel(0x1ffffff, adc->regs + ADC_INTRMASK_REG);
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/* Set default conversion interval */
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adc->interval = (clk_get_rate(adc->adc_clk) * 1000) / NSEC_PER_SEC;
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phytium_adc_power_setup(adc, true);
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return 0;
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}
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static void phytium_adc_intrmask_setup(struct phytium_adc *adc, unsigned long chan_mask, bool on)
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{
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u32 reg;
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u16 limit_mask = 0;
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int ch;
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for_each_set_bit(ch, &chan_mask, PHYTIUM_MAX_CHANNELS)
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limit_mask |= BIT(ch << 1) | BIT((ch << 1) + 1);
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reg = readl(adc->regs + ADC_INTRMASK_REG);
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if (on)
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reg &= ~(ADC_INTRMASK_REG_ERR_INTR_MASK |
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(limit_mask << 8) | chan_mask);
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else
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reg |= (ADC_INTRMASK_REG_ERR_INTR_MASK |
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(limit_mask << 8) | chan_mask);
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writel(reg, adc->regs + ADC_INTRMASK_REG);
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}
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static void phytium_adc_single_conv_setup(struct phytium_adc *adc, u8 ch)
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{
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u32 reg;
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/*
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* Setup control register:
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* - Single conversion mode selection
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* - Single conversion enable
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* - Fixed channel conversion
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* - Target channel
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*/
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reg = readl(adc->regs + ADC_CTRL_REG);
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/* Clean ch_only_s bits */
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reg &= ~ADC_CTRL_REG_CH_ONLY_S(7);
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/* Clean channel_en bit */
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reg &= 0xFFF00F;
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reg |= ADC_CTRL_REG_SINGLE_SEL | ADC_CTRL_REG_SINGLE_EN |
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ADC_CTRL_REG_CH_ONLY_EN | ADC_CTRL_REG_CH_ONLY_S(ch) | ADC_CTRL_REG_CHANNEL_EN(ch);
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writel(reg, adc->regs + ADC_CTRL_REG);
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}
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static int phytium_adc_single_conv(struct iio_dev *indio_dev, u8 ch)
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{
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struct phytium_adc *adc = iio_priv(indio_dev);
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int ret;
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ret = iio_device_claim_direct_mode(indio_dev);
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if (ret)
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return ret;
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mutex_lock(&adc->lock);
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phytium_adc_intrmask_setup(adc, BIT(ch), true);
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reinit_completion(&adc->completion);
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phytium_adc_single_conv_setup(adc, ch);
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phytium_adc_start_stop(adc, true);
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if (!wait_for_completion_timeout(&adc->completion, PHYTIUM_ADC_TIMEOUT))
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ret = -ETIMEDOUT;
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phytium_adc_start_stop(adc, false);
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phytium_adc_intrmask_setup(adc, BIT(ch), false);
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mutex_unlock(&adc->lock);
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iio_device_release_direct_mode(indio_dev);
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return ret;
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}
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static int phytium_adc_read_raw(struct iio_dev *indio_dev,
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struct iio_chan_spec const *chan,
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int *val, int *val2, long mask)
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{
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struct phytium_adc *adc = iio_priv(indio_dev);
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int ret;
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switch (mask) {
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case IIO_CHAN_INFO_RAW:
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if (chan->type != IIO_VOLTAGE)
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return -EINVAL;
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ret = phytium_adc_single_conv(indio_dev, chan->channel);
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if (ret)
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return ret;
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*val = adc->last_val[chan->channel];
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return IIO_VAL_INT;
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default:
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return -EINVAL;
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}
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}
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static int phytium_read_thresh(struct iio_dev *indio_dev,
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const struct iio_chan_spec *chan,
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enum iio_event_type type,
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enum iio_event_direction dir,
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enum iio_event_info iinfo, int *val, int *val2)
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{
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struct phytium_adc *adc = iio_priv(indio_dev);
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if (dir == IIO_EV_DIR_FALLING)
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*val = adc->thresh_low[chan->channel];
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else
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*val = adc->thresh_high[chan->channel];
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return IIO_VAL_INT;
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}
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static int phytium_write_thresh(struct iio_dev *indio_dev,
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const struct iio_chan_spec *chan,
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enum iio_event_type type,
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enum iio_event_direction dir,
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enum iio_event_info einfo, int val, int val2)
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{
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struct phytium_adc *adc = iio_priv(indio_dev);
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u32 thresh;
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switch (dir) {
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case IIO_EV_DIR_FALLING:
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adc->thresh_low[chan->channel] = val;
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thresh = readl(adc->regs + ADC_LEVEL_REG(chan->channel)) & 0x3ff0000;
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thresh |= ADC_LEVEL_REG_LOW_LEVEL(val);
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writel(thresh, adc->regs + ADC_LEVEL_REG(chan->channel));
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break;
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case IIO_EV_DIR_RISING:
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adc->thresh_high[chan->channel] = val;
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thresh = readl(adc->regs + ADC_LEVEL_REG(chan->channel)) & 0xffff;
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thresh |= ADC_LEVEL_REG_HIGH_LEVEL(val);
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writel(thresh, adc->regs + ADC_LEVEL_REG(chan->channel));
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static int phytium_update_scan_mode(struct iio_dev *indio_dev, const unsigned long *mask)
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{
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struct phytium_adc *adc = iio_priv(indio_dev);
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unsigned int n;
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n = bitmap_weight(mask, indio_dev->masklength);
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kfree(adc->scan_data);
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adc->scan_data = kcalloc(n, sizeof(*adc->scan_data), GFP_KERNEL);
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if (!adc->scan_data)
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return -ENOMEM;
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return 0;
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}
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static const u64 phytium_adc_event_codes[] = {
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IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 0,
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IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING),
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IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 0,
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IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING),
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IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 1,
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IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING),
|
||||
IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 1,
|
||||
IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING),
|
||||
IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 2,
|
||||
IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING),
|
||||
IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 2,
|
||||
IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING),
|
||||
IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 3,
|
||||
IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING),
|
||||
IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 3,
|
||||
IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING),
|
||||
IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 4,
|
||||
IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING),
|
||||
IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 4,
|
||||
IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING),
|
||||
IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 5,
|
||||
IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING),
|
||||
IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 5,
|
||||
IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING),
|
||||
IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 6,
|
||||
IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING),
|
||||
IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 6,
|
||||
IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING),
|
||||
IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 7,
|
||||
IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING),
|
||||
IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 7,
|
||||
IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING),
|
||||
};
|
||||
|
||||
static irqreturn_t phytium_adc_threaded_irq(int irq, void *data)
|
||||
{
|
||||
struct phytium_adc *adc = data;
|
||||
struct iio_dev *indio_dev = iio_priv_to_dev(adc);
|
||||
s64 timestamp = iio_get_time_ns(indio_dev);
|
||||
unsigned long status;
|
||||
int ch;
|
||||
u32 intr;
|
||||
|
||||
intr = readl(adc->regs + ADC_INTR_REG);
|
||||
|
||||
if (intr & ADC_INTR_REG_ERR) {
|
||||
dev_err(adc->dev, "conversion error: ADC_INTR_REG(0x%x)\n", intr);
|
||||
writel(ADC_INTR_REG_ERR, adc->regs + ADC_INTR_REG);
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
status = (intr & ADC_INTR_REG_LIMIT_MASK) >> 8;
|
||||
if (status) {
|
||||
for_each_set_bit(ch, &status, PHYTIUM_MAX_CHANNELS * 2)
|
||||
iio_push_event(indio_dev, phytium_adc_event_codes[ch], timestamp);
|
||||
}
|
||||
|
||||
status = intr & ADC_INTR_REG_COVFIN_MASK;
|
||||
if (status) {
|
||||
for_each_set_bit(ch, &status, PHYTIUM_MAX_CHANNELS)
|
||||
adc->last_val[ch] = readl(adc->regs + ADC_COV_RESULT_REG(ch)) &
|
||||
ADC_COV_RESULT_REG_MASK;
|
||||
|
||||
if (iio_buffer_enabled(indio_dev))
|
||||
iio_trigger_poll(indio_dev->trig);
|
||||
else
|
||||
complete(&adc->completion);
|
||||
}
|
||||
|
||||
/* Clear all the interrupts */
|
||||
writel(status, adc->regs + ADC_INTR_REG);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static void phytium_adc_cont_conv_setup(struct phytium_adc *adc,
|
||||
unsigned long chan_mask,
|
||||
u32 interval)
|
||||
{
|
||||
u32 reg;
|
||||
|
||||
/*
|
||||
* Setup control register:
|
||||
* - Continuous conversion mode
|
||||
* - Multi-channel rotation mode
|
||||
* - Channel enablement
|
||||
*/
|
||||
reg = readl(adc->regs + ADC_CTRL_REG);
|
||||
reg &= ~(ADC_CTRL_REG_SINGLE_SEL | ADC_CTRL_REG_SINGLE_EN |
|
||||
ADC_CTRL_REG_CH_ONLY_EN);
|
||||
reg |= chan_mask << 4;
|
||||
writel(reg, adc->regs + ADC_CTRL_REG);
|
||||
|
||||
/* Setup interval between two conversions */
|
||||
writel(interval, adc->regs + ADC_INTER_REG);
|
||||
}
|
||||
|
||||
static int phytium_adc_preenable(struct iio_dev *indio_dev)
|
||||
{
|
||||
struct phytium_adc *adc = iio_priv(indio_dev);
|
||||
unsigned long scan_mask = *indio_dev->active_scan_mask;
|
||||
|
||||
phytium_adc_cont_conv_setup(adc, scan_mask & 0xff, adc->interval);
|
||||
phytium_adc_intrmask_setup(adc, scan_mask & 0xff, true);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int phytium_adc_postenable(struct iio_dev *indio_dev)
|
||||
{
|
||||
struct phytium_adc *adc = iio_priv(indio_dev);
|
||||
|
||||
iio_triggered_buffer_postenable(indio_dev);
|
||||
phytium_adc_start_stop(adc, true);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int phytium_adc_postdisable(struct iio_dev *indio_dev)
|
||||
{
|
||||
struct phytium_adc *adc = iio_priv(indio_dev);
|
||||
unsigned long scan_mask = *indio_dev->active_scan_mask;
|
||||
|
||||
phytium_adc_start_stop(adc, false);
|
||||
phytium_adc_intrmask_setup(adc, scan_mask & 0xff, false);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct iio_buffer_setup_ops phytium_buffer_setup_ops = {
|
||||
.preenable = &phytium_adc_preenable,
|
||||
.postenable = &phytium_adc_postenable,
|
||||
.predisable = &iio_triggered_buffer_predisable,
|
||||
.postdisable = &phytium_adc_postdisable,
|
||||
};
|
||||
|
||||
static irqreturn_t phytium_adc_trigger_handler(int irq, void *p)
|
||||
{
|
||||
struct iio_poll_func *pf = p;
|
||||
struct iio_dev *indio_dev = pf->indio_dev;
|
||||
struct phytium_adc *adc = iio_priv(indio_dev);
|
||||
int i, j = 0;
|
||||
|
||||
if (!adc->scan_data)
|
||||
goto out;
|
||||
|
||||
for_each_set_bit(i, indio_dev->active_scan_mask, indio_dev->masklength)
|
||||
adc->scan_data[j++] = adc->last_val[i];
|
||||
|
||||
iio_push_to_buffers(indio_dev, adc->scan_data);
|
||||
|
||||
out:
|
||||
iio_trigger_notify_done(indio_dev->trig);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static const struct iio_info phytium_adc_iio_info = {
|
||||
.read_raw = &phytium_adc_read_raw,
|
||||
.read_event_value = &phytium_read_thresh,
|
||||
.write_event_value = &phytium_write_thresh,
|
||||
.update_scan_mode = &phytium_update_scan_mode,
|
||||
};
|
||||
|
||||
static int phytium_adc_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct phytium_adc *adc;
|
||||
struct iio_dev *indio_dev;
|
||||
struct device *dev = &pdev->dev;
|
||||
struct resource *res;
|
||||
int ret;
|
||||
|
||||
indio_dev = devm_iio_device_alloc(dev, sizeof(*adc));
|
||||
if (!indio_dev)
|
||||
return -ENOMEM;
|
||||
platform_set_drvdata(pdev, indio_dev);
|
||||
|
||||
adc = iio_priv(indio_dev);
|
||||
adc->dev = dev;
|
||||
|
||||
ret = phytium_adc_parse_properties(pdev, adc);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
mutex_init(&adc->lock);
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
adc->regs = devm_ioremap_resource(dev, res);
|
||||
if (IS_ERR(adc->regs))
|
||||
return PTR_ERR(adc->regs);
|
||||
|
||||
adc->adc_clk = devm_clk_get(dev, NULL);
|
||||
if (IS_ERR(adc->adc_clk))
|
||||
return PTR_ERR(adc->adc_clk);
|
||||
|
||||
init_completion(&adc->completion);
|
||||
|
||||
indio_dev->name = dev_name(dev);
|
||||
indio_dev->info = &phytium_adc_iio_info;
|
||||
indio_dev->modes = INDIO_DIRECT_MODE;
|
||||
indio_dev->channels = adc->data->channels;
|
||||
indio_dev->num_channels = adc->data->num_channels;
|
||||
|
||||
ret = devm_request_threaded_irq(adc->dev, platform_get_irq(pdev, 0),
|
||||
NULL, phytium_adc_threaded_irq, IRQF_ONESHOT,
|
||||
dev_name(dev), adc);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = devm_iio_triggered_buffer_setup(dev, indio_dev,
|
||||
&iio_pollfunc_store_time,
|
||||
phytium_adc_trigger_handler,
|
||||
&phytium_buffer_setup_ops);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = phytium_adc_hw_init(adc);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "failed to initialize Phytium ADC, %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
return devm_iio_device_register(dev, indio_dev);
|
||||
}
|
||||
|
||||
static int phytium_adc_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct iio_dev *indio_dev = platform_get_drvdata(pdev);
|
||||
struct phytium_adc *adc = iio_priv(indio_dev);
|
||||
|
||||
phytium_adc_power_setup(adc, false);
|
||||
iio_device_unregister(indio_dev);
|
||||
kfree(adc->scan_data);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id phytium_of_match[] = {
|
||||
{ .compatible = "phytium,adc", },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, phytium_of_match);
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
static int phytium_adc_suspend(struct device *dev)
|
||||
{
|
||||
struct iio_dev *indio_dev = dev_get_drvdata(dev);
|
||||
struct phytium_adc *adc = iio_priv(indio_dev);
|
||||
|
||||
phytium_adc_power_setup(adc, false);
|
||||
clk_disable_unprepare(adc->adc_clk);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int phytium_adc_resume(struct device *dev)
|
||||
{
|
||||
struct iio_dev *indio_dev = dev_get_drvdata(dev);
|
||||
struct phytium_adc *adc = iio_priv(indio_dev);
|
||||
|
||||
clk_prepare_enable(adc->adc_clk);
|
||||
phytium_adc_power_setup(adc, true);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
SIMPLE_DEV_PM_OPS(phytium_adc_pm_ops, phytium_adc_suspend, phytium_adc_resume);
|
||||
|
||||
static struct platform_driver phytium_adc_driver = {
|
||||
.driver = {
|
||||
.name = "phytium_adc",
|
||||
.of_match_table = phytium_of_match,
|
||||
.pm = &phytium_adc_pm_ops,
|
||||
},
|
||||
.probe = phytium_adc_probe,
|
||||
.remove = phytium_adc_remove,
|
||||
};
|
||||
module_platform_driver(phytium_adc_driver);
|
||||
|
||||
MODULE_AUTHOR("Yang Liu <yangliu2021@phytium.com.cn>");
|
||||
MODULE_DESCRIPTION("Phytium ADC driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
Loading…
Reference in New Issue