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parisc: improve SIGBUS/SIGSEGV error reporting 

This patch fixes most of the Linux Test Project testcases, e.g. fstat05.

Signed-off-by: Helge Deller <deller@gmx.de>
This commit is contained in:
Helge Deller 2013-11-18 22:12:11 +01:00
parent 38c7937379
commit 49d1cb2bca
1 changed files with 20 additions and 2 deletions
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22
arch/parisc/mm/fault.c
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@ -282,16 +282,34 @@ bad_area:
#endif #endif
switch (code) { switch (code) {
case 15: /* Data TLB miss fault/Data page fault */ case 15: /* Data TLB miss fault/Data page fault */
/* send SIGSEGV when outside of vma */
if (!vma ||
address < vma->vm_start || address > vma->vm_end) {
si.si_signo = SIGSEGV;
si.si_code = SEGV_MAPERR;
break;
}
/* send SIGSEGV for wrong permissions */
if ((vma->vm_flags & acc_type) != acc_type) {
si.si_signo = SIGSEGV;
si.si_code = SEGV_ACCERR;
break;
}
/* probably address is outside of mapped file */
/* fall through */
case 17: /* NA data TLB miss / page fault */ case 17: /* NA data TLB miss / page fault */
case 18: /* Unaligned access - PCXS only */ case 18: /* Unaligned access - PCXS only */
si.si_signo = SIGBUS; si.si_signo = SIGBUS;
si.si_code = BUS_ADRERR; si.si_code = (code == 18) ? BUS_ADRALN : BUS_ADRERR;
break; break;
case 16: /* Non-access instruction TLB miss fault */ case 16: /* Non-access instruction TLB miss fault */
case 26: /* PCXL: Data memory access rights trap */ case 26: /* PCXL: Data memory access rights trap */
default: default:
si.si_signo = SIGSEGV; si.si_signo = SIGSEGV;
si.si_code = SEGV_MAPERR; si.si_code = (code == 26) ? SEGV_ACCERR : SEGV_MAPERR;
break;
} }
si.si_errno = 0; si.si_errno = 0;
si.si_addr = (void __user *) address; si.si_addr = (void __user *) address;