arm64: dts: rockchip: add rk3328 iommu nodes
Add H265e/VEPU/VPU/VDEC/VOP iommu nodes Signed-off-by: Simon Xue <xxm@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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@ -520,6 +520,51 @@
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status = "disabled";
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};
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h265e_mmu: iommu@ff330200 {
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compatible = "rockchip,iommu";
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reg = <0x0 0xff330200 0 0x100>;
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interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "h265e_mmu";
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#iommu-cells = <0>;
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status = "disabled";
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};
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vepu_mmu: iommu@ff340800 {
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compatible = "rockchip,iommu";
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reg = <0x0 0xff340800 0x0 0x40>;
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interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "vepu_mmu";
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#iommu-cells = <0>;
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status = "disabled";
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};
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vpu_mmu: iommu@ff350800 {
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compatible = "rockchip,iommu";
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reg = <0x0 0xff350800 0x0 0x40>;
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "vpu_mmu";
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#iommu-cells = <0>;
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status = "disabled";
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};
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rkvdec_mmu: iommu@ff360480 {
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compatible = "rockchip,iommu";
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reg = <0x0 0xff360480 0x0 0x40>, <0x0 0xff3604c0 0x0 0x40>;
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interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "rkvdec_mmu";
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#iommu-cells = <0>;
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status = "disabled";
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};
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vop_mmu: iommu@ff373f00 {
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compatible = "rockchip,iommu";
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reg = <0x0 0xff373f00 0x0 0x100>;
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interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>;
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interrupt-names = "vop_mmu";
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#iommu-cells = <0>;
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status = "disabled";
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};
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cru: clock-controller@ff440000 {
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compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon";
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reg = <0x0 0xff440000 0x0 0x1000>;
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