GIC fixes for 4.5-rc4:
- Two fixes addressing cascaded GICv1/GICv2 (affinity setting, EOImode) - One fix addressing possible missed interrupts on GICv3 -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJWvGHfAAoJECPQ0LrRPXpDNXoQALNDEYgKuiaQBavpENKE6YSc rf+YT5KaWD5yzqZdITrxeGkkjCdTNiAS83/PIkQEH0QSqLE7lPJCl9o+u0uvT+Xb lrjqp9jGhmyiraZBrk68Sw4ySeNAqzLSw3pepLHpgt2dcwZSKS76XIu3kBmJnTo8 QGbYaH/2FyETlZk9aVTGAcTX3KMvFySd0OS/3gFaH/3rac7vSixzwX4TbMwbQRKj +yhEi0KIGIYm3pefkWwDxLSN/eBQH5NfLKg1oI2QduxwQwxr1pmG3A1SEe5LDKuA JxWfxmcrl2Un76cyDu3MiWpjpWCPiUtrK9M7OguZlo7R/wPvH00jqdlVPm13eagB Dy5kFW7QWaOLZ+jJCYn48gje/Fism0j8w5R6xAhMJuzqmuGmiZOwg/ff862DYlPz kRj8GFkgMlXZXy7yPxdSYlWtQPcaWAtRAY2XVFJtfk70RKOmX/GhYF7QDfZPnlX3 AfwjcyYvtILLKYcDYwdIfj5uQuxhC1+xoN9pp1eEQb38XHraL8ccUKIgeAwRK7xt S7H9yVhVbqmO5L4tBoG3v7S6H3NV3YWiAfd1iwOxrv8CyqILyIYQ9qE/sdhocMUB V2jZKKaiEaQR+QuKodEK6XXPl9ibpsIFnq/JisfT5JUCoIj27u7FnpMbmLZXwRHW UM3Tc0CwI3ypR7OpbOoq =FMCg -----END PGP SIGNATURE----- Merge tag 'gic-fixes-4.5-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into irq/urgent Pull GIC fixes from Marc for 4.5-rc4: - Two fixes addressing cascaded GICv1/GICv2 (affinity setting, EOImode) - One fix addressing possible missed interrupts on GICv3
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49b245efab
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@ -103,6 +103,7 @@ static inline u64 gic_read_iar_common(void)
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u64 irqstat;
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asm volatile("mrs_s %0, " __stringify(ICC_IAR1_EL1) : "=r" (irqstat));
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dsb(sy);
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return irqstat;
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}
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@ -384,9 +384,6 @@ static struct irq_chip gic_chip = {
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.irq_unmask = gic_unmask_irq,
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.irq_eoi = gic_eoi_irq,
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.irq_set_type = gic_set_type,
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#ifdef CONFIG_SMP
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.irq_set_affinity = gic_set_affinity,
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#endif
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.irq_get_irqchip_state = gic_irq_get_irqchip_state,
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.irq_set_irqchip_state = gic_irq_set_irqchip_state,
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.flags = IRQCHIP_SET_TYPE_MASKED |
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@ -400,9 +397,6 @@ static struct irq_chip gic_eoimode1_chip = {
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.irq_unmask = gic_unmask_irq,
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.irq_eoi = gic_eoimode1_eoi_irq,
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.irq_set_type = gic_set_type,
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#ifdef CONFIG_SMP
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.irq_set_affinity = gic_set_affinity,
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#endif
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.irq_get_irqchip_state = gic_irq_get_irqchip_state,
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.irq_set_irqchip_state = gic_irq_set_irqchip_state,
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.irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity,
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@ -443,7 +437,7 @@ static void gic_cpu_if_up(struct gic_chip_data *gic)
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u32 bypass = 0;
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u32 mode = 0;
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if (static_key_true(&supports_deactivate))
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if (gic == &gic_data[0] && static_key_true(&supports_deactivate))
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mode = GIC_CPU_CTRL_EOImodeNS;
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/*
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@ -1039,6 +1033,11 @@ static void __init __gic_init_bases(unsigned int gic_nr, int irq_start,
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gic->chip.name = kasprintf(GFP_KERNEL, "GIC-%d", gic_nr);
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}
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#ifdef CONFIG_SMP
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if (gic_nr == 0)
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gic->chip.irq_set_affinity = gic_set_affinity;
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#endif
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#ifdef CONFIG_GIC_NON_BANKED
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if (percpu_offset) { /* Frankein-GIC without banked registers... */
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unsigned int cpu;
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