GIC fixes for 4.5-rc4:

- Two fixes addressing cascaded GICv1/GICv2 (affinity setting, EOImode)
 - One fix addressing possible missed interrupts on GICv3
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJWvGHfAAoJECPQ0LrRPXpDNXoQALNDEYgKuiaQBavpENKE6YSc
 rf+YT5KaWD5yzqZdITrxeGkkjCdTNiAS83/PIkQEH0QSqLE7lPJCl9o+u0uvT+Xb
 lrjqp9jGhmyiraZBrk68Sw4ySeNAqzLSw3pepLHpgt2dcwZSKS76XIu3kBmJnTo8
 QGbYaH/2FyETlZk9aVTGAcTX3KMvFySd0OS/3gFaH/3rac7vSixzwX4TbMwbQRKj
 +yhEi0KIGIYm3pefkWwDxLSN/eBQH5NfLKg1oI2QduxwQwxr1pmG3A1SEe5LDKuA
 JxWfxmcrl2Un76cyDu3MiWpjpWCPiUtrK9M7OguZlo7R/wPvH00jqdlVPm13eagB
 Dy5kFW7QWaOLZ+jJCYn48gje/Fism0j8w5R6xAhMJuzqmuGmiZOwg/ff862DYlPz
 kRj8GFkgMlXZXy7yPxdSYlWtQPcaWAtRAY2XVFJtfk70RKOmX/GhYF7QDfZPnlX3
 AfwjcyYvtILLKYcDYwdIfj5uQuxhC1+xoN9pp1eEQb38XHraL8ccUKIgeAwRK7xt
 S7H9yVhVbqmO5L4tBoG3v7S6H3NV3YWiAfd1iwOxrv8CyqILyIYQ9qE/sdhocMUB
 V2jZKKaiEaQR+QuKodEK6XXPl9ibpsIFnq/JisfT5JUCoIj27u7FnpMbmLZXwRHW
 UM3Tc0CwI3ypR7OpbOoq
 =FMCg
 -----END PGP SIGNATURE-----

Merge tag 'gic-fixes-4.5-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into irq/urgent

Pull GIC fixes from Marc for 4.5-rc4:

- Two fixes addressing cascaded GICv1/GICv2 (affinity setting, EOImode)
- One fix addressing possible missed interrupts on GICv3
This commit is contained in:
Thomas Gleixner 2016-02-11 11:47:55 +01:00
commit 49b245efab
2 changed files with 7 additions and 7 deletions

View File

@ -103,6 +103,7 @@ static inline u64 gic_read_iar_common(void)
u64 irqstat;
asm volatile("mrs_s %0, " __stringify(ICC_IAR1_EL1) : "=r" (irqstat));
dsb(sy);
return irqstat;
}

View File

@ -384,9 +384,6 @@ static struct irq_chip gic_chip = {
.irq_unmask = gic_unmask_irq,
.irq_eoi = gic_eoi_irq,
.irq_set_type = gic_set_type,
#ifdef CONFIG_SMP
.irq_set_affinity = gic_set_affinity,
#endif
.irq_get_irqchip_state = gic_irq_get_irqchip_state,
.irq_set_irqchip_state = gic_irq_set_irqchip_state,
.flags = IRQCHIP_SET_TYPE_MASKED |
@ -400,9 +397,6 @@ static struct irq_chip gic_eoimode1_chip = {
.irq_unmask = gic_unmask_irq,
.irq_eoi = gic_eoimode1_eoi_irq,
.irq_set_type = gic_set_type,
#ifdef CONFIG_SMP
.irq_set_affinity = gic_set_affinity,
#endif
.irq_get_irqchip_state = gic_irq_get_irqchip_state,
.irq_set_irqchip_state = gic_irq_set_irqchip_state,
.irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity,
@ -443,7 +437,7 @@ static void gic_cpu_if_up(struct gic_chip_data *gic)
u32 bypass = 0;
u32 mode = 0;
if (static_key_true(&supports_deactivate))
if (gic == &gic_data[0] && static_key_true(&supports_deactivate))
mode = GIC_CPU_CTRL_EOImodeNS;
/*
@ -1039,6 +1033,11 @@ static void __init __gic_init_bases(unsigned int gic_nr, int irq_start,
gic->chip.name = kasprintf(GFP_KERNEL, "GIC-%d", gic_nr);
}
#ifdef CONFIG_SMP
if (gic_nr == 0)
gic->chip.irq_set_affinity = gic_set_affinity;
#endif
#ifdef CONFIG_GIC_NON_BANKED
if (percpu_offset) { /* Frankein-GIC without banked registers... */
unsigned int cpu;