drm/amdgpu: fix GFX10 missing CSIB set(v3)
still need to init csb even for SRIOV v2: drop init_pg() for gfx10 at all since PG and GFX off feature will be fully controled by RLC and SMU fw for gfx10 v3: drop the flush_gpu_tlb lines since we consider it is only usefull in emulation Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -1768,22 +1768,6 @@ static int gfx_v10_0_init_csb(struct amdgpu_device *adev)
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return 0;
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return 0;
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}
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}
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static int gfx_v10_0_init_pg(struct amdgpu_device *adev)
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{
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int i;
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int r;
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r = gfx_v10_0_init_csb(adev);
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if (r)
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return r;
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for (i = 0; i < adev->num_vmhubs; i++)
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amdgpu_gmc_flush_gpu_tlb(adev, 0, i, 0);
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/* TODO: init power gating */
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return 0;
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}
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void gfx_v10_0_rlc_stop(struct amdgpu_device *adev)
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void gfx_v10_0_rlc_stop(struct amdgpu_device *adev)
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{
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{
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u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
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u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
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@ -1876,21 +1860,16 @@ static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev)
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{
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{
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int r;
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int r;
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if (amdgpu_sriov_vf(adev))
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return 0;
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if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
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if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
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r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
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r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
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if (r)
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if (r)
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return r;
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return r;
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r = gfx_v10_0_init_pg(adev);
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gfx_v10_0_init_csb(adev);
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if (r)
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return r;
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/* enable RLC SRM */
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gfx_v10_0_rlc_enable_srm(adev);
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if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */
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gfx_v10_0_rlc_enable_srm(adev);
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} else {
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} else {
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adev->gfx.rlc.funcs->stop(adev);
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adev->gfx.rlc.funcs->stop(adev);
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@ -1912,9 +1891,7 @@ static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev)
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return r;
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return r;
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}
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}
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r = gfx_v10_0_init_pg(adev);
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gfx_v10_0_init_csb(adev);
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if (r)
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return r;
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adev->gfx.rlc.funcs->start(adev);
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adev->gfx.rlc.funcs->start(adev);
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