dt-bindings: display: bridge: Add i.MX8qm/qxp LVDS display bridge binding
This patch adds bindings for i.MX8qm/qxp LVDS display bridge(LDB). Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Liu Ying <victor.liu@nxp.com> Acked-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Robert Foss <robert.foss@linaro.org> Link: https://patchwork.freedesktop.org/patch/msgid/20220611141421.718743-11-victor.liu@nxp.com
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Liu Ying
Robert Foss
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1039fb6046
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48ed447c69
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-ldb.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Freescale i.MX8qm/qxp LVDS Display Bridge
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maintainers:
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- Liu Ying <victor.liu@nxp.com>
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description: |
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The Freescale i.MX8qm/qxp LVDS Display Bridge(LDB) has two channels.
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The i.MX8qm/qxp LDB is controlled by Control and Status Registers(CSR) module.
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The CSR module, as a system controller, contains the LDB's configuration
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registers.
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For i.MX8qxp LDB, each channel supports up to 24bpp parallel input color
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format and can map the input to VESA or JEIDA standards. The two channels
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cannot be used simultaneously, that is to say, the user should pick one of
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them to use. Two LDB channels from two LDB instances can work together in
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LDB split mode to support a dual link LVDS display. The channel indexes
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have to be different. Channel0 outputs odd pixels and channel1 outputs
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even pixels.
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For i.MX8qm LDB, each channel additionally supports up to 30bpp parallel
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input color format. The two channels can be used simultaneously, either
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in dual mode or split mode. In dual mode, the two channels output identical
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data. In split mode, channel0 outputs odd pixels and channel1 outputs even
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pixels.
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A side note is that i.MX8qm/qxp LDB is officially called pixel mapper in
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the SoC reference manuals. The pixel mapper uses logic of LDBs embedded in
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i.MX6qdl/sx SoCs, i.e., it is essentially based on them. To keep the naming
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consistency, this binding calls it LDB.
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properties:
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compatible:
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enum:
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- fsl,imx8qm-ldb
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- fsl,imx8qxp-ldb
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"#address-cells":
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const: 1
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"#size-cells":
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const: 0
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clocks:
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items:
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- description: pixel clock
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- description: bypass clock
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clock-names:
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items:
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- const: pixel
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- const: bypass
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power-domains:
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maxItems: 1
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fsl,companion-ldb:
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$ref: /schemas/types.yaml#/definitions/phandle
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description: |
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A phandle which points to companion LDB which is used in LDB split mode.
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patternProperties:
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"^channel@[0-1]$":
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type: object
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description: Represents a channel of LDB.
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properties:
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"#address-cells":
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const: 1
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"#size-cells":
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const: 0
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reg:
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description: The channel index.
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enum: [ 0, 1 ]
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phys:
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description: A phandle to the phy module representing the LVDS PHY.
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maxItems: 1
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phy-names:
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const: lvds_phy
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port@0:
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$ref: /schemas/graph.yaml#/properties/port
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description: Input port of the channel.
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port@1:
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$ref: /schemas/graph.yaml#/properties/port
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description: Output port of the channel.
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required:
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- "#address-cells"
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- "#size-cells"
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- reg
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- phys
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- phy-names
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additionalProperties: false
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required:
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- compatible
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- "#address-cells"
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- "#size-cells"
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- clocks
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- clock-names
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- power-domains
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- channel@0
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- channel@1
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allOf:
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- if:
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properties:
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compatible:
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contains:
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const: fsl,imx8qm-ldb
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then:
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properties:
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fsl,companion-ldb: false
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/firmware/imx/rsrc.h>
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ldb {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx8qxp-ldb";
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clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_MISC2>,
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<&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_BYPASS>;
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clock-names = "pixel", "bypass";
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power-domains = <&pd IMX_SC_R_LVDS_0>;
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channel@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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phys = <&mipi_lvds_0_phy>;
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phy-names = "lvds_phy";
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port@0 {
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reg = <0>;
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mipi_lvds_0_ldb_ch0_mipi_lvds_0_pxl2dpi: endpoint {
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remote-endpoint = <&mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch0>;
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};
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};
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};
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channel@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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phys = <&mipi_lvds_0_phy>;
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phy-names = "lvds_phy";
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port@0 {
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reg = <0>;
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mipi_lvds_0_ldb_ch1_mipi_lvds_0_pxl2dpi: endpoint {
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remote-endpoint = <&mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch1>;
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};
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};
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};
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};
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