RDMA/mlx5: Use mlx5_umr_post_send_wait() to rereg pd access
Move rereg_pd_access logic to umr.c, and use mlx5_umr_post_send_wait() instead of mlx5_ib_post_send_wait(). Link: https://lore.kernel.org/r/18da4f47edbc2561f652b7ee4e7a5269e866af77.1649747695.git.leonro@nvidia.com Signed-off-by: Aharon Landau <aharonl@nvidia.com> Reviewed-by: Michael Guralnik <michaelgur@nvidia.com> Signed-off-by: Leon Romanovsky <leonro@nvidia.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
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@ -1646,30 +1646,6 @@ static bool can_use_umr_rereg_access(struct mlx5_ib_dev *dev,
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target_access_flags);
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target_access_flags);
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}
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}
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static int umr_rereg_pd_access(struct mlx5_ib_mr *mr, struct ib_pd *pd,
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int access_flags)
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{
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struct mlx5_ib_dev *dev = to_mdev(mr->ibmr.device);
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struct mlx5_umr_wr umrwr = {
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.wr = {
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.send_flags = MLX5_IB_SEND_UMR_FAIL_IF_FREE |
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MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS,
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.opcode = MLX5_IB_WR_UMR,
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},
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.mkey = mr->mmkey.key,
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.pd = pd,
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.access_flags = access_flags,
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};
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int err;
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err = mlx5_ib_post_send_wait(dev, &umrwr);
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if (err)
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return err;
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mr->access_flags = access_flags;
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return 0;
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}
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static bool can_use_umr_rereg_pas(struct mlx5_ib_mr *mr,
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static bool can_use_umr_rereg_pas(struct mlx5_ib_mr *mr,
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struct ib_umem *new_umem,
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struct ib_umem *new_umem,
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int new_access_flags, u64 iova,
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int new_access_flags, u64 iova,
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@ -1770,7 +1746,8 @@ struct ib_mr *mlx5_ib_rereg_user_mr(struct ib_mr *ib_mr, int flags, u64 start,
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/* Fast path for PD/access change */
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/* Fast path for PD/access change */
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if (can_use_umr_rereg_access(dev, mr->access_flags,
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if (can_use_umr_rereg_access(dev, mr->access_flags,
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new_access_flags)) {
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new_access_flags)) {
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err = umr_rereg_pd_access(mr, new_pd, new_access_flags);
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err = mlx5r_umr_rereg_pd_access(mr, new_pd,
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new_access_flags);
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if (err)
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if (err)
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return ERR_PTR(err);
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return ERR_PTR(err);
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return NULL;
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return NULL;
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@ -349,3 +349,44 @@ int mlx5r_umr_revoke_mr(struct mlx5_ib_mr *mr)
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return mlx5r_umr_post_send_wait(dev, mr->mmkey.key, &wqe, false);
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return mlx5r_umr_post_send_wait(dev, mr->mmkey.key, &wqe, false);
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}
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}
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static void mlx5r_umr_set_access_flags(struct mlx5_ib_dev *dev,
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struct mlx5_mkey_seg *seg,
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unsigned int access_flags)
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{
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MLX5_SET(mkc, seg, a, !!(access_flags & IB_ACCESS_REMOTE_ATOMIC));
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MLX5_SET(mkc, seg, rw, !!(access_flags & IB_ACCESS_REMOTE_WRITE));
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MLX5_SET(mkc, seg, rr, !!(access_flags & IB_ACCESS_REMOTE_READ));
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MLX5_SET(mkc, seg, lw, !!(access_flags & IB_ACCESS_LOCAL_WRITE));
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MLX5_SET(mkc, seg, lr, 1);
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MLX5_SET(mkc, seg, relaxed_ordering_write,
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!!(access_flags & IB_ACCESS_RELAXED_ORDERING));
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MLX5_SET(mkc, seg, relaxed_ordering_read,
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!!(access_flags & IB_ACCESS_RELAXED_ORDERING));
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}
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int mlx5r_umr_rereg_pd_access(struct mlx5_ib_mr *mr, struct ib_pd *pd,
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int access_flags)
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{
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struct mlx5_ib_dev *dev = mr_to_mdev(mr);
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struct mlx5r_umr_wqe wqe = {};
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int err;
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wqe.ctrl_seg.mkey_mask = get_umr_update_access_mask(dev);
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wqe.ctrl_seg.mkey_mask |= get_umr_update_pd_mask();
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wqe.ctrl_seg.flags = MLX5_UMR_CHECK_FREE;
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wqe.ctrl_seg.flags |= MLX5_UMR_INLINE;
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mlx5r_umr_set_access_flags(dev, &wqe.mkey_seg, access_flags);
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MLX5_SET(mkc, &wqe.mkey_seg, pd, to_mpd(pd)->pdn);
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MLX5_SET(mkc, &wqe.mkey_seg, qpn, 0xffffff);
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MLX5_SET(mkc, &wqe.mkey_seg, mkey_7_0,
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mlx5_mkey_variant(mr->mmkey.key));
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err = mlx5r_umr_post_send_wait(dev, mr->mmkey.key, &wqe, false);
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if (err)
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return err;
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mr->access_flags = access_flags;
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return 0;
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}
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@ -92,5 +92,7 @@ struct mlx5r_umr_wqe {
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};
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};
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int mlx5r_umr_revoke_mr(struct mlx5_ib_mr *mr);
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int mlx5r_umr_revoke_mr(struct mlx5_ib_mr *mr);
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int mlx5r_umr_rereg_pd_access(struct mlx5_ib_mr *mr, struct ib_pd *pd,
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int access_flags);
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#endif /* _MLX5_IB_UMR_H */
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#endif /* _MLX5_IB_UMR_H */
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