rtw88: add dynamic rrsr configuration
Register rrsr determines the response rate we send. In field tests, using rate higher than current tx rate could lead to difficulty for the receiving end to receive management/control frames. Calculate current modulation level by tx rate then cross out rate higher than those. Signed-off-by: Po-Hao Huang <phhuang@realtek.com> Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Reviewed-by: Brian Norris <briannorris@chromium.org> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/20210209070755.23019-2-pkshih@realtek.com
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@ -894,6 +894,7 @@ static u64 rtw_update_rate_mask(struct rtw_dev *rtwdev,
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void rtw_update_sta_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si)
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{
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struct rtw_dm_info *dm_info = &rtwdev->dm_info;
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struct ieee80211_sta *sta = si->sta;
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struct rtw_efuse *efuse = &rtwdev->efuse;
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struct rtw_hal *hal = &rtwdev->hal;
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@ -938,6 +939,7 @@ void rtw_update_sta_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si)
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} else {
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wireless_set = WIRELESS_OFDM;
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}
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dm_info->rrsr_val_init = RRSR_INIT_5G;
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} else if (hal->current_band_type == RTW_BAND_2G) {
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ra_mask |= sta->supp_rates[NL80211_BAND_2GHZ];
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if (sta->vht_cap.vht_supported) {
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@ -955,6 +957,7 @@ void rtw_update_sta_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si)
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} else {
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wireless_set = WIRELESS_CCK | WIRELESS_OFDM;
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}
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dm_info->rrsr_val_init = RRSR_INIT_2G;
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} else {
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rtw_err(rtwdev, "Unknown band type\n");
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wireless_set = 0;
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@ -1495,6 +1495,9 @@ struct rtw_iqk_info {
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} result;
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};
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#define RRSR_INIT_2G 0x15f
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#define RRSR_INIT_5G 0x150
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struct rtw_dm_info {
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u32 cck_fa_cnt;
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u32 ofdm_fa_cnt;
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@ -1525,6 +1528,8 @@ struct rtw_dm_info {
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u8 cck_gi_l_bnd;
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u8 tx_rate;
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u32 rrsr_val_init;
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u32 rrsr_mask_min;
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u8 thermal_avg[RTW_RF_PATH_MAX];
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u8 thermal_meter_k;
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s8 delta_power_index[RTW_RF_PATH_MAX];
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@ -465,6 +465,60 @@ static void rtw_phy_ra_info_update(struct rtw_dev *rtwdev)
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rtw_iterate_stas_atomic(rtwdev, rtw_phy_ra_info_update_iter, rtwdev);
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}
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static u32 rtw_phy_get_rrsr_mask(struct rtw_dev *rtwdev, u8 rate_idx)
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{
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u8 rate_order;
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rate_order = rate_idx;
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if (rate_idx >= DESC_RATEVHT4SS_MCS0)
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rate_order -= DESC_RATEVHT4SS_MCS0;
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else if (rate_idx >= DESC_RATEVHT3SS_MCS0)
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rate_order -= DESC_RATEVHT3SS_MCS0;
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else if (rate_idx >= DESC_RATEVHT2SS_MCS0)
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rate_order -= DESC_RATEVHT2SS_MCS0;
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else if (rate_idx >= DESC_RATEVHT1SS_MCS0)
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rate_order -= DESC_RATEVHT1SS_MCS0;
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else if (rate_idx >= DESC_RATEMCS24)
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rate_order -= DESC_RATEMCS24;
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else if (rate_idx >= DESC_RATEMCS16)
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rate_order -= DESC_RATEMCS16;
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else if (rate_idx >= DESC_RATEMCS8)
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rate_order -= DESC_RATEMCS8;
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else if (rate_idx >= DESC_RATEMCS0)
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rate_order -= DESC_RATEMCS0;
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else if (rate_idx >= DESC_RATE6M)
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rate_order -= DESC_RATE6M;
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else
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rate_order -= DESC_RATE1M;
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if (rate_idx >= DESC_RATEMCS0 || rate_order == 0)
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rate_order++;
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return GENMASK(rate_order + RRSR_RATE_ORDER_CCK_LEN - 1, 0);
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}
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static void rtw_phy_rrsr_mask_min_iter(void *data, struct ieee80211_sta *sta)
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{
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struct rtw_dev *rtwdev = (struct rtw_dev *)data;
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struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv;
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struct rtw_dm_info *dm_info = &rtwdev->dm_info;
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u32 mask = 0;
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mask = rtw_phy_get_rrsr_mask(rtwdev, si->ra_report.desc_rate);
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if (mask < dm_info->rrsr_mask_min)
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dm_info->rrsr_mask_min = mask;
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}
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static void rtw_phy_rrsr_update(struct rtw_dev *rtwdev)
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{
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struct rtw_dm_info *dm_info = &rtwdev->dm_info;
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dm_info->rrsr_mask_min = RRSR_RATE_ORDER_MAX;
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rtw_iterate_stas_atomic(rtwdev, rtw_phy_rrsr_mask_min_iter, rtwdev);
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rtw_write32(rtwdev, REG_RRSR, dm_info->rrsr_val_init & dm_info->rrsr_mask_min);
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}
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static void rtw_phy_dpk_track(struct rtw_dev *rtwdev)
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{
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struct rtw_chip_info *chip = rtwdev->chip;
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@ -561,13 +615,19 @@ static void rtw_phy_pwr_track(struct rtw_dev *rtwdev)
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rtwdev->chip->ops->pwr_track(rtwdev);
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}
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static void rtw_phy_ra_track(struct rtw_dev *rtwdev)
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{
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rtw_phy_ra_info_update(rtwdev);
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rtw_phy_rrsr_update(rtwdev);
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}
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void rtw_phy_dynamic_mechanism(struct rtw_dev *rtwdev)
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{
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/* for further calculation */
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rtw_phy_statistics(rtwdev);
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rtw_phy_dig(rtwdev);
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rtw_phy_cck_pd(rtwdev);
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rtw_phy_ra_info_update(rtwdev);
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rtw_phy_ra_track(rtwdev);
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rtw_phy_dpk_track(rtwdev);
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rtw_phy_pwr_track(rtwdev);
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}
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@ -185,4 +185,7 @@ enum rtw_phy_cck_pd_lv {
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#define LSSI_READ_EDGE_MASK 0x80000000
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#define LSSI_READ_DATA_MASK 0xfffff
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#define RRSR_RATE_ORDER_MAX 0xfffff
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#define RRSR_RATE_ORDER_CCK_LEN 4
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#endif
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@ -306,6 +306,8 @@
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#define REG_DARFRC 0x0430
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#define REG_DARFRCH 0x0434
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#define REG_RARFRCH 0x043C
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#define REG_RRSR 0x0440
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#define BITS_RRSR_RSC GENMASK(22, 21)
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#define REG_ARFR0 0x0444
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#define REG_ARFRH0 0x0448
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#define REG_ARFR1_V1 0x044C
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@ -164,8 +164,6 @@ const struct rtw_table name ## _tbl = { \
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#define REG_ANAPARLDO_POW_MAC 0x0029
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#define BIT_LDOE25_PON BIT(0)
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#define REG_RRSR 0x0440
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#define BITS_RRSR_RSC (BIT(21) | BIT(22))
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#define REG_TXDFIR0 0x808
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#define REG_DFIRBW 0x810
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