drm/amd/display: Set max TTU on DPG enable
[WHY] There is a bug in HW that causes P-State to hang when DPG is enabled in certain conditions. [HOW] The solution is to force MIN_TTU_VBLANK register to maximum value whenever DPG has been enabled. Make stream do a full update on test pattern change, so that the TTUs get updated. When DPG is enabled, update the ttu_regs.min_ttu_vblank field of each pipe in the stream's topology to the maximum value (0xffffff). v2: squash in build fix for when DCN is not defined (Alex) Signed-off-by: Wesley Chalmers <Wesley.Chalmers@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -49,6 +49,7 @@
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#include "timing_generator.h"
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#include "abm.h"
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#include "virtual/virtual_link_encoder.h"
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#include "hubp.h"
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#include "link_hwss.h"
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#include "link_encoder.h"
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@ -2095,6 +2096,10 @@ static enum surface_update_type check_update_surfaces_for_stream(
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if (stream_status == NULL || stream_status->plane_count != surface_count)
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overall_type = UPDATE_TYPE_FULL;
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if (stream_update && stream_update->pending_test_pattern) {
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overall_type = UPDATE_TYPE_FULL;
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}
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/* some stream updates require passive update */
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if (stream_update) {
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union stream_update_flags *su_flags = &stream_update->stream->update_flags;
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@ -2491,6 +2496,14 @@ static void commit_planes_do_stream_update(struct dc *dc,
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}
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}
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/* Full fe update*/
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if (update_type == UPDATE_TYPE_FAST)
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continue;
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if (stream_update->dsc_config)
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dp_update_dsc_config(pipe_ctx);
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if (stream_update->pending_test_pattern) {
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dc_link_dp_set_test_pattern(stream->link,
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stream->test_pattern.type,
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@ -2500,13 +2513,6 @@ static void commit_planes_do_stream_update(struct dc *dc,
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stream->test_pattern.cust_pattern_size);
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}
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/* Full fe update*/
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if (update_type == UPDATE_TYPE_FAST)
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continue;
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if (stream_update->dsc_config)
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dp_update_dsc_config(pipe_ctx);
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if (stream_update->dpms_off) {
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if (*stream_update->dpms_off) {
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core_link_disable_stream(pipe_ctx);
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@ -2593,6 +2599,17 @@ static void commit_planes_for_stream(struct dc *dc,
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}
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}
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#ifdef CONFIG_DRM_AMD_DC_DCN
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if (stream->test_pattern.type != DP_TEST_PATTERN_VIDEO_MODE) {
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struct pipe_ctx *mpcc_pipe;
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struct pipe_ctx *odm_pipe;
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for (mpcc_pipe = top_pipe_to_program; mpcc_pipe; mpcc_pipe = mpcc_pipe->bottom_pipe)
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for (odm_pipe = mpcc_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
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odm_pipe->ttu_regs.min_ttu_vblank = MAX_TTU;
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}
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#endif
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if ((update_type != UPDATE_TYPE_FAST) && stream->update_flags.bits.dsc_changed)
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if (top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_enable) {
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if (should_use_dmub_lock(stream->link)) {
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@ -29,6 +29,7 @@
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#include "mem_input.h"
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#define OPP_ID_INVALID 0xf
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#define MAX_TTU 0xffffff
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enum cursor_pitch {
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