drm/exynos: Fix build breakage on !DRM_EXYNOS_FIMD
Disabling the CONFIG_DRM_EXYNOS_FIMD (e.g. by enabling of CONFIG_FB_S3C) leads to build error: drivers/built-in.o: In function `exynos_dp_dpms': binder.c:(.text+0xd6a840): undefined reference to `fimd_dp_clock_enable' binder.c:(.text+0xd6ab54): undefined reference to `fimd_dp_clock_enable' Fix this by changing direct call to fimd_dp_clock_enable() into optional call to exynos_drm_crtc_ops->clock_enable(). Only the DRM_EXYNOS_FIMD implements this op. Signed-off-by: Krzysztof Kozlowski <k.kozlowski.k@gmail.com> Reviewed-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Tested-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Signed-off-by: Inki Dae <inki.dae@samsung.com>
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@ -32,7 +32,6 @@
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#include <drm/bridge/ptn3460.h>
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#include "exynos_dp_core.h"
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#include "exynos_drm_fimd.h"
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#define ctx_from_connector(c) container_of(c, struct exynos_dp_device, \
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connector)
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@ -1066,6 +1065,8 @@ static void exynos_dp_phy_exit(struct exynos_dp_device *dp)
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static void exynos_dp_poweron(struct exynos_dp_device *dp)
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{
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struct exynos_drm_crtc *crtc = dp_to_crtc(dp);
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if (dp->dpms_mode == DRM_MODE_DPMS_ON)
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return;
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@ -1076,7 +1077,8 @@ static void exynos_dp_poweron(struct exynos_dp_device *dp)
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}
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}
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fimd_dp_clock_enable(dp_to_crtc(dp), true);
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if (crtc->ops->clock_enable)
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crtc->ops->clock_enable(dp_to_crtc(dp), true);
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clk_prepare_enable(dp->clock);
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exynos_dp_phy_init(dp);
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@ -1087,6 +1089,8 @@ static void exynos_dp_poweron(struct exynos_dp_device *dp)
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static void exynos_dp_poweroff(struct exynos_dp_device *dp)
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{
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struct exynos_drm_crtc *crtc = dp_to_crtc(dp);
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if (dp->dpms_mode != DRM_MODE_DPMS_ON)
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return;
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@ -1102,7 +1106,8 @@ static void exynos_dp_poweroff(struct exynos_dp_device *dp)
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exynos_dp_phy_exit(dp);
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clk_disable_unprepare(dp->clock);
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fimd_dp_clock_enable(dp_to_crtc(dp), false);
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if (crtc->ops->clock_enable)
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crtc->ops->clock_enable(dp_to_crtc(dp), false);
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if (dp->panel) {
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if (drm_panel_unprepare(dp->panel))
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@ -181,6 +181,10 @@ struct exynos_drm_display {
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* @win_disable: disable hardware specific overlay.
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* @te_handler: trigger to transfer video image at the tearing effect
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* synchronization signal if there is a page flip request.
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* @clock_enable: optional function enabling/disabling display domain clock,
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* called from exynos-dp driver before powering up (with
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* 'enable' argument as true) and after powering down (with
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* 'enable' as false).
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*/
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struct exynos_drm_crtc;
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struct exynos_drm_crtc_ops {
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@ -195,6 +199,7 @@ struct exynos_drm_crtc_ops {
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void (*win_commit)(struct exynos_drm_crtc *crtc, unsigned int zpos);
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void (*win_disable)(struct exynos_drm_crtc *crtc, unsigned int zpos);
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void (*te_handler)(struct exynos_drm_crtc *crtc);
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void (*clock_enable)(struct exynos_drm_crtc *crtc, bool enable);
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};
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/*
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@ -33,7 +33,6 @@
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#include "exynos_drm_crtc.h"
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#include "exynos_drm_plane.h"
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#include "exynos_drm_iommu.h"
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#include "exynos_drm_fimd.h"
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/*
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* FIMD stands for Fully Interactive Mobile Display and
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@ -946,6 +945,23 @@ static void fimd_te_handler(struct exynos_drm_crtc *crtc)
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drm_handle_vblank(ctx->drm_dev, ctx->pipe);
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}
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static void fimd_dp_clock_enable(struct exynos_drm_crtc *crtc, bool enable)
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{
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struct fimd_context *ctx = crtc->ctx;
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u32 val;
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/*
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* Only Exynos 5250, 5260, 5410 and 542x requires enabling DP/MIE
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* clock. On these SoCs the bootloader may enable it but any
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* power domain off/on will reset it to disable state.
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*/
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if (ctx->driver_data != &exynos5_fimd_driver_data)
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return;
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val = enable ? DP_MIE_CLK_DP_ENABLE : DP_MIE_CLK_DISABLE;
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writel(DP_MIE_CLK_DP_ENABLE, ctx->regs + DP_MIE_CLKCON);
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}
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static struct exynos_drm_crtc_ops fimd_crtc_ops = {
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.dpms = fimd_dpms,
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.mode_fixup = fimd_mode_fixup,
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@ -956,6 +972,7 @@ static struct exynos_drm_crtc_ops fimd_crtc_ops = {
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.win_commit = fimd_win_commit,
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.win_disable = fimd_win_disable,
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.te_handler = fimd_te_handler,
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.clock_enable = fimd_dp_clock_enable,
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};
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static irqreturn_t fimd_irq_handler(int irq, void *dev_id)
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@ -1192,24 +1209,6 @@ static int fimd_remove(struct platform_device *pdev)
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return 0;
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}
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void fimd_dp_clock_enable(struct exynos_drm_crtc *crtc, bool enable)
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{
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struct fimd_context *ctx = crtc->ctx;
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u32 val;
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/*
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* Only Exynos 5250, 5260, 5410 and 542x requires enabling DP/MIE
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* clock. On these SoCs the bootloader may enable it but any
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* power domain off/on will reset it to disable state.
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*/
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if (ctx->driver_data != &exynos5_fimd_driver_data)
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return;
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val = enable ? DP_MIE_CLK_DP_ENABLE : DP_MIE_CLK_DISABLE;
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writel(DP_MIE_CLK_DP_ENABLE, ctx->regs + DP_MIE_CLKCON);
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}
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EXPORT_SYMBOL_GPL(fimd_dp_clock_enable);
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struct platform_driver fimd_driver = {
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.probe = fimd_probe,
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.remove = fimd_remove,
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@ -1,15 +0,0 @@
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/*
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* Copyright (c) 2015 Samsung Electronics Co., Ltd.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#ifndef _EXYNOS_DRM_FIMD_H_
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#define _EXYNOS_DRM_FIMD_H_
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extern void fimd_dp_clock_enable(struct exynos_drm_crtc *crtc, bool enable);
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#endif /* _EXYNOS_DRM_FIMD_H_ */
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