drm/i915: Compute DSI PLL parameters during .compute_config()
Compute the DSI PLL parameters during .compute_config() rather than .pre_pll_enable() so that we can fail gracefully if we can't find suitable parameters. In order to do that we need to store the DSI PLL parameters in pipe_config. v2: Handle BXT too Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1460488478-18311-3-git-send-email-ville.syrjala@linux.intel.com Tested-by: Jani Nikula <jani.nikula@intel.com>
This commit is contained in:
Ville Syrjälä
parent
cd2d34d9b6
commit
47eacbabcb
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@ -12763,6 +12763,9 @@ intel_pipe_config_compare(struct drm_device *dev,
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PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
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PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
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PIPE_CONF_CHECK_X(dsi_pll.ctrl);
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PIPE_CONF_CHECK_X(dsi_pll.div);
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if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
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PIPE_CONF_CHECK_I(pipe_bpp);
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@ -497,6 +497,11 @@ struct intel_crtc_state {
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/* Actual register state of the dpll, for shared dpll cross-checking. */
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struct intel_dpll_hw_state dpll_hw_state;
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/* DSI PLL registers */
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struct {
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u32 ctrl, div;
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} dsi_pll;
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int pipe_bpp;
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struct intel_link_m_n dp_m_n;
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@ -292,6 +292,7 @@ static bool intel_dsi_compute_config(struct intel_encoder *encoder,
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struct intel_connector *intel_connector = intel_dsi->attached_connector;
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struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
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struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
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int ret;
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DRM_DEBUG_KMS("\n");
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@ -311,10 +312,10 @@ static bool intel_dsi_compute_config(struct intel_encoder *encoder,
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pipe_config->cpu_transcoder = TRANSCODER_DSI_A;
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}
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/*
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* FIXME move the DSI PLL calc from vlv_enable_dsi_pll()
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* to .compute_config().
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*/
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ret = intel_compute_dsi_pll(encoder, pipe_config);
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if (ret)
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return false;
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pipe_config->clock_set = true;
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return true;
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@ -504,6 +505,7 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder)
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struct drm_device *dev = encoder->base.dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
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struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
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enum port port;
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u32 tmp;
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@ -514,7 +516,7 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder)
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* lock. It needs to be fully powered down to fix it.
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*/
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intel_disable_dsi_pll(encoder);
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intel_enable_dsi_pll(encoder);
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intel_enable_dsi_pll(encoder, crtc->config);
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intel_dsi_prepare(encoder);
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@ -824,7 +826,8 @@ static void intel_dsi_get_config(struct intel_encoder *encoder,
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if (IS_BROXTON(dev))
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bxt_dsi_get_pipe_config(encoder, pipe_config);
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pclk = intel_dsi_get_pclk(encoder, pipe_config->pipe_bpp);
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pclk = intel_dsi_get_pclk(encoder, pipe_config->pipe_bpp,
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pipe_config);
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if (!pclk)
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return;
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@ -127,11 +127,15 @@ static inline struct intel_dsi *enc_to_intel_dsi(struct drm_encoder *encoder)
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}
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bool intel_dsi_pll_is_enabled(struct drm_i915_private *dev_priv);
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extern void intel_enable_dsi_pll(struct intel_encoder *encoder);
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extern void intel_disable_dsi_pll(struct intel_encoder *encoder);
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extern u32 intel_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp);
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extern void intel_dsi_reset_clocks(struct intel_encoder *encoder,
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enum port port);
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int intel_compute_dsi_pll(struct intel_encoder *encoder,
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struct intel_crtc_state *config);
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void intel_enable_dsi_pll(struct intel_encoder *encoder,
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const struct intel_crtc_state *config);
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void intel_disable_dsi_pll(struct intel_encoder *encoder);
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u32 intel_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp,
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struct intel_crtc_state *config);
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void intel_dsi_reset_clocks(struct intel_encoder *encoder,
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enum port port);
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struct drm_panel *vbt_panel_init(struct intel_dsi *intel_dsi, u16 panel_id);
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enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt);
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@ -30,11 +30,6 @@
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#include "i915_drv.h"
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#include "intel_dsi.h"
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struct dsi_mnp {
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u32 dsi_pll_ctrl;
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u32 dsi_pll_div;
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};
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static const u16 lfsr_converts[] = {
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426, 469, 234, 373, 442, 221, 110, 311, 411, /* 62 - 70 */
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461, 486, 243, 377, 188, 350, 175, 343, 427, 213, /* 71 - 80 */
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@ -57,7 +52,8 @@ static u32 dsi_clk_from_pclk(u32 pclk, enum mipi_dsi_pixel_format fmt,
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}
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static int dsi_calc_mnp(struct drm_i915_private *dev_priv,
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struct dsi_mnp *dsi_mnp, int target_dsi_clk)
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struct intel_crtc_state *config,
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int target_dsi_clk)
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{
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unsigned int calc_m = 0, calc_p = 0;
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unsigned int m_min, m_max, p_min = 2, p_max = 6;
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@ -103,8 +99,8 @@ static int dsi_calc_mnp(struct drm_i915_private *dev_priv,
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/* register has log2(N1), this works fine for powers of two */
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n = ffs(n) - 1;
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m_seed = lfsr_converts[calc_m - 62];
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dsi_mnp->dsi_pll_ctrl = 1 << (DSI_PLL_P1_POST_DIV_SHIFT + calc_p - 2);
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dsi_mnp->dsi_pll_div = n << DSI_PLL_N1_DIV_SHIFT |
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config->dsi_pll.ctrl = 1 << (DSI_PLL_P1_POST_DIV_SHIFT + calc_p - 2);
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config->dsi_pll.div = n << DSI_PLL_N1_DIV_SHIFT |
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m_seed << DSI_PLL_M1_DIV_SHIFT;
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return 0;
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@ -114,54 +110,63 @@ static int dsi_calc_mnp(struct drm_i915_private *dev_priv,
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* XXX: The muxing and gating is hard coded for now. Need to add support for
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* sharing PLLs with two DSI outputs.
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*/
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static void vlv_configure_dsi_pll(struct intel_encoder *encoder)
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static int vlv_compute_dsi_pll(struct intel_encoder *encoder,
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struct intel_crtc_state *config)
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{
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struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
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struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
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int ret;
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struct dsi_mnp dsi_mnp;
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u32 dsi_clk;
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dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format,
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intel_dsi->lane_count);
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ret = dsi_calc_mnp(dev_priv, &dsi_mnp, dsi_clk);
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ret = dsi_calc_mnp(dev_priv, config, dsi_clk);
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if (ret) {
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DRM_DEBUG_KMS("dsi_calc_mnp failed\n");
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return;
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return ret;
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}
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if (intel_dsi->ports & (1 << PORT_A))
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dsi_mnp.dsi_pll_ctrl |= DSI_PLL_CLK_GATE_DSI0_DSIPLL;
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config->dsi_pll.ctrl |= DSI_PLL_CLK_GATE_DSI0_DSIPLL;
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if (intel_dsi->ports & (1 << PORT_C))
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dsi_mnp.dsi_pll_ctrl |= DSI_PLL_CLK_GATE_DSI1_DSIPLL;
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config->dsi_pll.ctrl |= DSI_PLL_CLK_GATE_DSI1_DSIPLL;
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config->dsi_pll.ctrl |= DSI_PLL_VCO_EN;
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DRM_DEBUG_KMS("dsi pll div %08x, ctrl %08x\n",
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dsi_mnp.dsi_pll_div, dsi_mnp.dsi_pll_ctrl);
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config->dsi_pll.div, config->dsi_pll.ctrl);
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vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, 0);
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vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_DIVIDER, dsi_mnp.dsi_pll_div);
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vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, dsi_mnp.dsi_pll_ctrl);
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return 0;
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}
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static void vlv_enable_dsi_pll(struct intel_encoder *encoder)
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static void vlv_configure_dsi_pll(struct intel_encoder *encoder,
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const struct intel_crtc_state *config)
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{
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struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
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u32 tmp;
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struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, 0);
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vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_DIVIDER, config->dsi_pll.div);
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vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL,
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config->dsi_pll.ctrl & ~DSI_PLL_VCO_EN);
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}
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static void vlv_enable_dsi_pll(struct intel_encoder *encoder,
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const struct intel_crtc_state *config)
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{
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struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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DRM_DEBUG_KMS("\n");
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mutex_lock(&dev_priv->sb_lock);
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vlv_configure_dsi_pll(encoder);
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vlv_configure_dsi_pll(encoder, config);
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/* wait at least 0.5 us after ungating before enabling VCO */
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usleep_range(1, 10);
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tmp = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
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tmp |= DSI_PLL_VCO_EN;
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vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, tmp);
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vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, config->dsi_pll.ctrl);
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if (wait_for(vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL) &
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DSI_PLL_LOCK, 20)) {
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@ -177,7 +182,7 @@ static void vlv_enable_dsi_pll(struct intel_encoder *encoder)
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static void vlv_disable_dsi_pll(struct intel_encoder *encoder)
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{
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struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
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struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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u32 tmp;
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DRM_DEBUG_KMS("\n");
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@ -224,7 +229,7 @@ static bool bxt_dsi_pll_is_enabled(struct drm_i915_private *dev_priv)
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static void bxt_disable_dsi_pll(struct intel_encoder *encoder)
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{
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struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
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struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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u32 val;
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DRM_DEBUG_KMS("\n");
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@ -251,9 +256,10 @@ static void assert_bpp_mismatch(enum mipi_dsi_pixel_format fmt, int pipe_bpp)
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bpp, pipe_bpp);
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}
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static u32 vlv_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp)
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static u32 vlv_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp,
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struct intel_crtc_state *config)
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{
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struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
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struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
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u32 dsi_clock, pclk;
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u32 pll_ctl, pll_div;
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@ -268,6 +274,9 @@ static u32 vlv_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp)
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pll_div = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_DIVIDER);
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mutex_unlock(&dev_priv->sb_lock);
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config->dsi_pll.ctrl = pll_ctl & ~DSI_PLL_LOCK;
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config->dsi_pll.div = pll_div;
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/* mask out other bits and extract the P1 divisor */
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pll_ctl &= DSI_PLL_P1_POST_DIV_MASK;
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pll_ctl = pll_ctl >> (DSI_PLL_P1_POST_DIV_SHIFT - 2);
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@ -313,7 +322,8 @@ static u32 vlv_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp)
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return pclk;
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}
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static u32 bxt_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp)
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static u32 bxt_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp,
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struct intel_crtc_state *config)
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{
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u32 pclk;
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u32 dsi_clk;
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@ -327,15 +337,9 @@ static u32 bxt_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp)
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return 0;
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}
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dsi_ratio = I915_READ(BXT_DSI_PLL_CTL) &
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BXT_DSI_PLL_RATIO_MASK;
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config->dsi_pll.ctrl = I915_READ(BXT_DSI_PLL_CTL);
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/* Invalid DSI ratio ? */
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if (dsi_ratio < BXT_DSI_PLL_RATIO_MIN ||
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dsi_ratio > BXT_DSI_PLL_RATIO_MAX) {
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DRM_ERROR("Invalid DSI pll ratio(%u) programmed\n", dsi_ratio);
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return 0;
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}
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dsi_ratio = config->dsi_pll.ctrl & BXT_DSI_PLL_RATIO_MASK;
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dsi_clk = (dsi_ratio * BXT_REF_CLOCK_KHZ) / 2;
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@ -348,12 +352,13 @@ static u32 bxt_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp)
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return pclk;
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}
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u32 intel_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp)
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u32 intel_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp,
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struct intel_crtc_state *config)
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{
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if (IS_BROXTON(encoder->base.dev))
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return bxt_dsi_get_pclk(encoder, pipe_bpp);
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return bxt_dsi_get_pclk(encoder, pipe_bpp, config);
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else
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return vlv_dsi_get_pclk(encoder, pipe_bpp);
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return vlv_dsi_get_pclk(encoder, pipe_bpp, config);
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}
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static void vlv_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
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@ -370,7 +375,8 @@ static void vlv_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
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}
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/* Program BXT Mipi clocks and dividers */
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static void bxt_dsi_program_clocks(struct drm_device *dev, enum port port)
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static void bxt_dsi_program_clocks(struct drm_device *dev, enum port port,
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const struct intel_crtc_state *config)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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u32 tmp;
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@ -390,8 +396,7 @@ static void bxt_dsi_program_clocks(struct drm_device *dev, enum port port)
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tmp &= ~(BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port));
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/* Get the current DSI rate(actual) */
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pll_ratio = I915_READ(BXT_DSI_PLL_CTL) &
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BXT_DSI_PLL_RATIO_MASK;
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pll_ratio = config->dsi_pll.ctrl & BXT_DSI_PLL_RATIO_MASK;
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dsi_rate = (BXT_REF_CLOCK_KHZ * pll_ratio) / 2;
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/*
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@ -427,16 +432,15 @@ static void bxt_dsi_program_clocks(struct drm_device *dev, enum port port)
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I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp);
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}
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static bool bxt_configure_dsi_pll(struct intel_encoder *encoder)
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static int bxt_compute_dsi_pll(struct intel_encoder *encoder,
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struct intel_crtc_state *config)
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{
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struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
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struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
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u8 dsi_ratio;
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u32 dsi_clk;
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u32 val;
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dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format,
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intel_dsi->lane_count);
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intel_dsi->lane_count);
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/*
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* From clock diagram, to get PLL ratio divider, divide double of DSI
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@ -445,9 +449,9 @@ static bool bxt_configure_dsi_pll(struct intel_encoder *encoder)
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*/
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dsi_ratio = DIV_ROUND_UP(dsi_clk * 2, BXT_REF_CLOCK_KHZ);
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if (dsi_ratio < BXT_DSI_PLL_RATIO_MIN ||
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dsi_ratio > BXT_DSI_PLL_RATIO_MAX) {
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dsi_ratio > BXT_DSI_PLL_RATIO_MAX) {
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DRM_ERROR("Cant get a suitable ratio from DSI PLL ratios\n");
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return false;
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return -ECHRNG;
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}
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/*
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@ -455,27 +459,28 @@ static bool bxt_configure_dsi_pll(struct intel_encoder *encoder)
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* Spec says both have to be programmed, even if one is not getting
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* used. Configure MIPI_CLOCK_CTL dividers in modeset
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*/
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val = I915_READ(BXT_DSI_PLL_CTL);
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val &= ~BXT_DSI_PLL_PVD_RATIO_MASK;
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val &= ~BXT_DSI_FREQ_SEL_MASK;
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val &= ~BXT_DSI_PLL_RATIO_MASK;
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val |= (dsi_ratio | BXT_DSIA_16X_BY2 | BXT_DSIC_16X_BY2);
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config->dsi_pll.ctrl = dsi_ratio | BXT_DSIA_16X_BY2 | BXT_DSIC_16X_BY2;
|
||||
|
||||
/* As per recommendation from hardware team,
|
||||
* Prog PVD ratio =1 if dsi ratio <= 50
|
||||
*/
|
||||
if (dsi_ratio <= 50) {
|
||||
val &= ~BXT_DSI_PLL_PVD_RATIO_MASK;
|
||||
val |= BXT_DSI_PLL_PVD_RATIO_1;
|
||||
}
|
||||
if (dsi_ratio <= 50)
|
||||
config->dsi_pll.ctrl |= BXT_DSI_PLL_PVD_RATIO_1;
|
||||
|
||||
I915_WRITE(BXT_DSI_PLL_CTL, val);
|
||||
POSTING_READ(BXT_DSI_PLL_CTL);
|
||||
|
||||
return true;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void bxt_enable_dsi_pll(struct intel_encoder *encoder)
|
||||
static void bxt_configure_dsi_pll(struct intel_encoder *encoder,
|
||||
const struct intel_crtc_state *config)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
||||
|
||||
I915_WRITE(BXT_DSI_PLL_CTL, config->dsi_pll.ctrl);
|
||||
POSTING_READ(BXT_DSI_PLL_CTL);
|
||||
}
|
||||
|
||||
static void bxt_enable_dsi_pll(struct intel_encoder *encoder,
|
||||
const struct intel_crtc_state *config)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
|
||||
struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
|
||||
|
|
@ -485,14 +490,11 @@ static void bxt_enable_dsi_pll(struct intel_encoder *encoder)
|
|||
DRM_DEBUG_KMS("\n");
|
||||
|
||||
/* Configure PLL vales */
|
||||
if (!bxt_configure_dsi_pll(encoder)) {
|
||||
DRM_ERROR("Configure DSI PLL failed, abort PLL enable\n");
|
||||
return;
|
||||
}
|
||||
bxt_configure_dsi_pll(encoder, config);
|
||||
|
||||
/* Program TX, RX, Dphy clocks */
|
||||
for_each_dsi_port(port, intel_dsi->ports)
|
||||
bxt_dsi_program_clocks(encoder->base.dev, port);
|
||||
bxt_dsi_program_clocks(encoder->base.dev, port, config);
|
||||
|
||||
/* Enable DSI PLL */
|
||||
val = I915_READ(BXT_DSI_PLL_ENABLE);
|
||||
|
|
@ -518,14 +520,28 @@ bool intel_dsi_pll_is_enabled(struct drm_i915_private *dev_priv)
|
|||
return false;
|
||||
}
|
||||
|
||||
void intel_enable_dsi_pll(struct intel_encoder *encoder)
|
||||
int intel_compute_dsi_pll(struct intel_encoder *encoder,
|
||||
struct intel_crtc_state *config)
|
||||
{
|
||||
struct drm_device *dev = encoder->base.dev;
|
||||
|
||||
if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
|
||||
vlv_enable_dsi_pll(encoder);
|
||||
return vlv_compute_dsi_pll(encoder, config);
|
||||
else if (IS_BROXTON(dev))
|
||||
bxt_enable_dsi_pll(encoder);
|
||||
return bxt_compute_dsi_pll(encoder, config);
|
||||
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
void intel_enable_dsi_pll(struct intel_encoder *encoder,
|
||||
const struct intel_crtc_state *config)
|
||||
{
|
||||
struct drm_device *dev = encoder->base.dev;
|
||||
|
||||
if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
|
||||
vlv_enable_dsi_pll(encoder, config);
|
||||
else if (IS_BROXTON(dev))
|
||||
bxt_enable_dsi_pll(encoder, config);
|
||||
}
|
||||
|
||||
void intel_disable_dsi_pll(struct intel_encoder *encoder)
|
||||
|
|
|
|||
Loading…
Reference in New Issue