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drm/amd/pp: Replace function/struct name cz_* with smu8_* 

hw ip smu8 was used on CZ/ST,
so use smu8 as the prefix of the function/struct name in powerplay.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Rex Zhu 2018-03-14 17:29:54 +08:00 committed by Alex Deucher
parent ce1ace35b7
commit 47ce4a9f84
5 changed files with 805 additions and 806 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

888
drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
View File

File diff suppressed because it is too large Load Diff

71
drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.h
View File

@ -21,18 +21,18 @@
*
*/
#ifndef _CZ_HWMGR_H_
#define _CZ_HWMGR_H_
#ifndef _SMU8_HWMGR_H_
#define _SMU8_HWMGR_H_
#include "cgs_common.h"
#include "ppatomctrl.h"
#define CZ_NUM_NBPSTATES 4
#define CZ_NUM_NBPMEMORYCLOCK 2
#define SMU8_NUM_NBPSTATES 4
#define SMU8_NUM_NBPMEMORYCLOCK 2
#define MAX_DISPLAY_CLOCK_LEVEL 8
#define CZ_MAX_HARDWARE_POWERLEVELS 8
#define PPCZ_VOTINGRIGHTSCLIENTS_DFLT0 0x3FFFC102
#define CZ_MIN_DEEP_SLEEP_SCLK 800
#define SMU8_MAX_HARDWARE_POWERLEVELS 8
#define SMU8_VOTINGRIGHTSCLIENTS_DFLT0 0x3FFFC102
#define SMU8_MIN_DEEP_SLEEP_SCLK 800
/* Carrizo device IDs */
#define DEVICE_ID_CZ_9870 0x9870
@ -41,24 +41,21 @@
#define DEVICE_ID_CZ_9876 0x9876
#define DEVICE_ID_CZ_9877 0x9877
#define PHMCZ_WRITE_SMC_REGISTER(device, reg, value) \
cgs_write_ind_register(device, CGS_IND_REG__SMC, ix##reg, value)
struct cz_dpm_entry {
struct smu8_dpm_entry {
uint32_t soft_min_clk;
uint32_t hard_min_clk;
uint32_t soft_max_clk;
uint32_t hard_max_clk;
};
struct cz_sys_info {
struct smu8_sys_info {
uint32_t bootup_uma_clock;
uint32_t bootup_engine_clock;
uint32_t dentist_vco_freq;
uint32_t nb_dpm_enable;
uint32_t nbp_memory_clock[CZ_NUM_NBPMEMORYCLOCK];
uint32_t nbp_n_clock[CZ_NUM_NBPSTATES];
uint16_t nbp_voltage_index[CZ_NUM_NBPSTATES];
uint32_t nbp_memory_clock[SMU8_NUM_NBPMEMORYCLOCK];
uint32_t nbp_n_clock[SMU8_NUM_NBPSTATES];
uint16_t nbp_voltage_index[SMU8_NUM_NBPSTATES];
uint32_t display_clock[MAX_DISPLAY_CLOCK_LEVEL];
uint16_t bootup_nb_voltage_index;
uint8_t htc_tmp_lmt;
@ -85,21 +82,21 @@ struct cz_sys_info {
((tx) ? DISPLAYPHY_TX_SELECT : 0) | \
((core) ? DISPLAYPHY_CORE_SELECT : 0))
struct cz_display_phy_info_entry {
struct smu8_display_phy_info_entry {
uint8_t phy_present;
uint8_t active_lane_mapping;
uint8_t display_config_type;
uint8_t active_number_of_lanes;
};
#define CZ_MAX_DISPLAYPHY_IDS 10
#define SMU8_MAX_DISPLAYPHY_IDS 10
struct cz_display_phy_info {
struct smu8_display_phy_info {
bool display_phy_access_initialized;
struct cz_display_phy_info_entry entries[CZ_MAX_DISPLAYPHY_IDS];
struct smu8_display_phy_info_entry entries[SMU8_MAX_DISPLAYPHY_IDS];
};
struct cz_power_level {
struct smu8_power_level {
uint32_t engineClock;
uint8_t vddcIndex;
uint8_t dsDividerIndex;
@ -113,7 +110,7 @@ struct cz_power_level {
uint8_t rsv[3];
};
struct cz_uvd_clocks {
struct smu8_uvd_clocks {
uint32_t vclk;
uint32_t dclk;
uint32_t vclk_low_divider;
@ -122,7 +119,7 @@ struct cz_uvd_clocks {
uint32_t dclk_high_divider;
};
enum cz_pstate_previous_action {
enum smu8_pstate_previous_action {
DO_NOTHING = 1,
FORCE_HIGH,
CANCEL_FORCE_HIGH
@ -143,10 +140,10 @@ struct pp_disable_nb_ps_flags {
};
};
struct cz_power_state {
struct smu8_power_state {
unsigned int magic;
uint32_t level;
struct cz_uvd_clocks uvd_clocks;
struct smu8_uvd_clocks uvd_clocks;
uint32_t evclk;
uint32_t ecclk;
uint32_t samclk;
@ -158,8 +155,8 @@ struct cz_power_state {
uint8_t dpm_0_pg_nb_ps_high;
uint8_t dpm_x_nb_ps_low;
uint8_t dpm_x_nb_ps_high;
enum cz_pstate_previous_action action;
struct cz_power_level levels[CZ_MAX_HARDWARE_POWERLEVELS];
enum smu8_pstate_previous_action action;
struct smu8_power_level levels[SMU8_MAX_HARDWARE_POWERLEVELS];
struct pp_disable_nb_ps_flags disable_nb_ps_flag;
};
@ -182,7 +179,7 @@ struct cc6_settings {
uint32_t cpu_pstate_separation_time;
};
struct cz_hwmgr {
struct smu8_hwmgr {
uint32_t dpm_interval;
uint32_t voltage_drop_threshold;
@ -202,11 +199,11 @@ struct cz_hwmgr {
uint32_t thermal_auto_throttling_treshold;
struct cz_sys_info sys_info;
struct smu8_sys_info sys_info;
struct cz_power_level boot_power_level;
struct cz_power_state *cz_current_ps;
struct cz_power_state *cz_requested_ps;
struct smu8_power_level boot_power_level;
struct smu8_power_state *smu8_current_ps;
struct smu8_power_state *smu8_requested_ps;
uint32_t mgcg_cgtt_local0;
uint32_t mgcg_cgtt_local1;
@ -219,7 +216,7 @@ struct cz_hwmgr {
uint32_t lock_nb_ps_in_uvd_play_back;
struct cz_display_phy_info display_phy_info;
struct smu8_display_phy_info display_phy_info;
uint32_t vce_slow_sclk_threshold; /* default 200mhz */
uint32_t dce_slow_sclk_threshold; /* default 300mhz */
uint32_t min_sclk_did; /* minimum sclk divider */
@ -270,10 +267,10 @@ struct cz_hwmgr {
uint32_t fps_low_threshold;
uint32_t dpm_flags;
struct cz_dpm_entry sclk_dpm;
struct cz_dpm_entry uvd_dpm;
struct cz_dpm_entry vce_dpm;
struct cz_dpm_entry acp_dpm;
struct smu8_dpm_entry sclk_dpm;
struct smu8_dpm_entry uvd_dpm;
struct smu8_dpm_entry vce_dpm;
struct smu8_dpm_entry acp_dpm;
uint8_t uvd_boot_level;
uint8_t vce_boot_level;
@ -311,4 +308,4 @@ struct cz_hwmgr {
uint32_t num_of_clk_entries;
};
#endif /* _CZ_HWMGR_H_ */
#endif /* _SMU8_HWMGR_H_ */

8
drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
View File

@ -35,7 +35,7 @@
#include "pp_psm.h"
extern const struct pp_smumgr_func ci_smu_funcs;
extern const struct pp_smumgr_func cz_smu_funcs;
extern const struct pp_smumgr_func smu8_smu_funcs;
extern const struct pp_smumgr_func iceland_smu_funcs;
extern const struct pp_smumgr_func tonga_smu_funcs;
extern const struct pp_smumgr_func fiji_smu_funcs;
@ -44,7 +44,7 @@ extern const struct pp_smumgr_func vega10_smu_funcs;
extern const struct pp_smumgr_func smu10_smu_funcs;
extern int smu7_init_function_pointers(struct pp_hwmgr *hwmgr);
extern int cz_init_function_pointers(struct pp_hwmgr *hwmgr);
extern int smu8_init_function_pointers(struct pp_hwmgr *hwmgr);
extern int vega10_hwmgr_init(struct pp_hwmgr *hwmgr);
extern int smu10_init_function_pointers(struct pp_hwmgr *hwmgr);
@ -144,8 +144,8 @@ int hwmgr_early_init(struct pp_hwmgr *hwmgr)
break;
case AMDGPU_FAMILY_CZ:
hwmgr->od_enabled = false;
hwmgr->smumgr_funcs = &cz_smu_funcs;
cz_init_function_pointers(hwmgr);
hwmgr->smumgr_funcs = &smu8_smu_funcs;
smu8_init_function_pointers(hwmgr);
break;
case AMDGPU_FAMILY_VI:
switch (hwmgr->chip_id) {

562
drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c
View File

@ -41,18 +41,18 @@
#define SIZE_ALIGN_32(x) (((x) + 31) / 32 * 32)
static const enum cz_scratch_entry firmware_list[] = {
CZ_SCRATCH_ENTRY_UCODE_ID_SDMA0,
CZ_SCRATCH_ENTRY_UCODE_ID_SDMA1,
CZ_SCRATCH_ENTRY_UCODE_ID_CP_CE,
CZ_SCRATCH_ENTRY_UCODE_ID_CP_PFP,
CZ_SCRATCH_ENTRY_UCODE_ID_CP_ME,
CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1,
CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT2,
CZ_SCRATCH_ENTRY_UCODE_ID_RLC_G,
static const enum smu8_scratch_entry firmware_list[] = {
SMU8_SCRATCH_ENTRY_UCODE_ID_SDMA0,
SMU8_SCRATCH_ENTRY_UCODE_ID_SDMA1,
SMU8_SCRATCH_ENTRY_UCODE_ID_CP_CE,
SMU8_SCRATCH_ENTRY_UCODE_ID_CP_PFP,
SMU8_SCRATCH_ENTRY_UCODE_ID_CP_ME,
SMU8_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1,
SMU8_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT2,
SMU8_SCRATCH_ENTRY_UCODE_ID_RLC_G,
};
static int cz_smum_get_argument(struct pp_hwmgr *hwmgr)
static int smu8_smum_get_argument(struct pp_hwmgr *hwmgr)
{
if (hwmgr == NULL || hwmgr->device == NULL)
return -EINVAL;
@ -61,7 +61,7 @@ static int cz_smum_get_argument(struct pp_hwmgr *hwmgr)
mmSMU_MP1_SRBM2P_ARG_0);
}
static int cz_send_msg_to_smc_async(struct pp_hwmgr *hwmgr, uint16_t msg)
static int smu8_send_msg_to_smc_async(struct pp_hwmgr *hwmgr, uint16_t msg)
{
int result = 0;
@ -71,7 +71,7 @@ static int cz_send_msg_to_smc_async(struct pp_hwmgr *hwmgr, uint16_t msg)
result = PHM_WAIT_FIELD_UNEQUAL(hwmgr,
SMU_MP1_SRBM2P_RESP_0, CONTENT, 0);
if (result != 0) {
pr_err("cz_send_msg_to_smc_async (0x%04x) failed\n", msg);
pr_err("smu8_send_msg_to_smc_async (0x%04x) failed\n", msg);
return result;
}
@ -82,11 +82,11 @@ static int cz_send_msg_to_smc_async(struct pp_hwmgr *hwmgr, uint16_t msg)
}
/* Send a message to the SMC, and wait for its response.*/
static int cz_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg)
static int smu8_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg)
{
int result = 0;
result = cz_send_msg_to_smc_async(hwmgr, msg);
result = smu8_send_msg_to_smc_async(hwmgr, msg);
if (result != 0)
return result;
@ -94,7 +94,7 @@ static int cz_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg)
SMU_MP1_SRBM2P_RESP_0, CONTENT, 0);
}
static int cz_set_smc_sram_address(struct pp_hwmgr *hwmgr,
static int smu8_set_smc_sram_address(struct pp_hwmgr *hwmgr,
uint32_t smc_address, uint32_t limit)
{
if (hwmgr == NULL || hwmgr->device == NULL)
@ -116,7 +116,7 @@ static int cz_set_smc_sram_address(struct pp_hwmgr *hwmgr,
return 0;
}
static int cz_write_smc_sram_dword(struct pp_hwmgr *hwmgr,
static int smu8_write_smc_sram_dword(struct pp_hwmgr *hwmgr,
uint32_t smc_address, uint32_t value, uint32_t limit)
{
int result;
@ -124,14 +124,14 @@ static int cz_write_smc_sram_dword(struct pp_hwmgr *hwmgr,
if (hwmgr == NULL || hwmgr->device == NULL)
return -EINVAL;
result = cz_set_smc_sram_address(hwmgr, smc_address, limit);
result = smu8_set_smc_sram_address(hwmgr, smc_address, limit);
if (!result)
cgs_write_register(hwmgr->device, mmMP0PUB_IND_DATA_0, value);
return result;
}
static int cz_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr,
static int smu8_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr,
uint16_t msg, uint32_t parameter)
{
if (hwmgr == NULL || hwmgr->device == NULL)
@ -139,10 +139,10 @@ static int cz_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr,
cgs_write_register(hwmgr->device, mmSMU_MP1_SRBM2P_ARG_0, parameter);
return cz_send_msg_to_smc(hwmgr, msg);
return smu8_send_msg_to_smc(hwmgr, msg);
}
static int cz_check_fw_load_finish(struct pp_hwmgr *hwmgr,
static int smu8_check_fw_load_finish(struct pp_hwmgr *hwmgr,
uint32_t firmware)
{
int i;
@ -170,18 +170,18 @@ static int cz_check_fw_load_finish(struct pp_hwmgr *hwmgr,
return 0;
}
static int cz_load_mec_firmware(struct pp_hwmgr *hwmgr)
static int smu8_load_mec_firmware(struct pp_hwmgr *hwmgr)
{
uint32_t reg_data;
uint32_t tmp;
int ret = 0;
struct cgs_firmware_info info = {0};
struct cz_smumgr *cz_smu;
struct smu8_smumgr *smu8_smu;
if (hwmgr == NULL || hwmgr->device == NULL)
return -EINVAL;
cz_smu = hwmgr->smu_backend;
smu8_smu = hwmgr->smu_backend;
ret = cgs_get_firmware_info(hwmgr->device,
CGS_UCODE_ID_CP_MEC, &info);
@ -215,72 +215,72 @@ static int cz_load_mec_firmware(struct pp_hwmgr *hwmgr)
return 0;
}
static uint8_t cz_translate_firmware_enum_to_arg(struct pp_hwmgr *hwmgr,
enum cz_scratch_entry firmware_enum)
static uint8_t smu8_translate_firmware_enum_to_arg(struct pp_hwmgr *hwmgr,
enum smu8_scratch_entry firmware_enum)
{
uint8_t ret = 0;
switch (firmware_enum) {
case CZ_SCRATCH_ENTRY_UCODE_ID_SDMA0:
case SMU8_SCRATCH_ENTRY_UCODE_ID_SDMA0:
ret = UCODE_ID_SDMA0;
break;
case CZ_SCRATCH_ENTRY_UCODE_ID_SDMA1:
case SMU8_SCRATCH_ENTRY_UCODE_ID_SDMA1:
if (hwmgr->chip_id == CHIP_STONEY)
ret = UCODE_ID_SDMA0;
else
ret = UCODE_ID_SDMA1;
break;
case CZ_SCRATCH_ENTRY_UCODE_ID_CP_CE:
case SMU8_SCRATCH_ENTRY_UCODE_ID_CP_CE:
ret = UCODE_ID_CP_CE;
break;
case CZ_SCRATCH_ENTRY_UCODE_ID_CP_PFP:
case SMU8_SCRATCH_ENTRY_UCODE_ID_CP_PFP:
ret = UCODE_ID_CP_PFP;
break;
case CZ_SCRATCH_ENTRY_UCODE_ID_CP_ME:
case SMU8_SCRATCH_ENTRY_UCODE_ID_CP_ME:
ret = UCODE_ID_CP_ME;
break;
case CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1:
case SMU8_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1:
ret = UCODE_ID_CP_MEC_JT1;
break;
case CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT2:
case SMU8_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT2:
if (hwmgr->chip_id == CHIP_STONEY)
ret = UCODE_ID_CP_MEC_JT1;
else
ret = UCODE_ID_CP_MEC_JT2;
break;
case CZ_SCRATCH_ENTRY_UCODE_ID_GMCON_RENG:
case SMU8_SCRATCH_ENTRY_UCODE_ID_GMCON_RENG:
ret = UCODE_ID_GMCON_RENG;
break;
case CZ_SCRATCH_ENTRY_UCODE_ID_RLC_G:
case SMU8_SCRATCH_ENTRY_UCODE_ID_RLC_G:
ret = UCODE_ID_RLC_G;
break;
case CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SCRATCH:
case SMU8_SCRATCH_ENTRY_UCODE_ID_RLC_SCRATCH:
ret = UCODE_ID_RLC_SCRATCH;
break;
case CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_ARAM:
case SMU8_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_ARAM:
ret = UCODE_ID_RLC_SRM_ARAM;
break;
case CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_DRAM:
case SMU8_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_DRAM:
ret = UCODE_ID_RLC_SRM_DRAM;
break;
case CZ_SCRATCH_ENTRY_UCODE_ID_DMCU_ERAM:
case SMU8_SCRATCH_ENTRY_UCODE_ID_DMCU_ERAM:
ret = UCODE_ID_DMCU_ERAM;
break;
case CZ_SCRATCH_ENTRY_UCODE_ID_DMCU_IRAM:
case SMU8_SCRATCH_ENTRY_UCODE_ID_DMCU_IRAM:
ret = UCODE_ID_DMCU_IRAM;
break;
case CZ_SCRATCH_ENTRY_UCODE_ID_POWER_PROFILING:
case SMU8_SCRATCH_ENTRY_UCODE_ID_POWER_PROFILING:
ret = TASK_ARG_INIT_MM_PWR_LOG;
break;
case CZ_SCRATCH_ENTRY_DATA_ID_SDMA_HALT:
case CZ_SCRATCH_ENTRY_DATA_ID_SYS_CLOCKGATING:
case CZ_SCRATCH_ENTRY_DATA_ID_SDMA_RING_REGS:
case CZ_SCRATCH_ENTRY_DATA_ID_NONGFX_REINIT:
case CZ_SCRATCH_ENTRY_DATA_ID_SDMA_START:
case CZ_SCRATCH_ENTRY_DATA_ID_IH_REGISTERS:
case SMU8_SCRATCH_ENTRY_DATA_ID_SDMA_HALT:
case SMU8_SCRATCH_ENTRY_DATA_ID_SYS_CLOCKGATING:
case SMU8_SCRATCH_ENTRY_DATA_ID_SDMA_RING_REGS:
case SMU8_SCRATCH_ENTRY_DATA_ID_NONGFX_REINIT:
case SMU8_SCRATCH_ENTRY_DATA_ID_SDMA_START:
case SMU8_SCRATCH_ENTRY_DATA_ID_IH_REGISTERS:
ret = TASK_ARG_REG_MMIO;
break;
case CZ_SCRATCH_ENTRY_SMU8_FUSION_CLKTABLE:
case SMU8_SCRATCH_ENTRY_SMU8_FUSION_CLKTABLE:
ret = TASK_ARG_INIT_CLK_TABLE;
break;
}
@ -288,7 +288,7 @@ static uint8_t cz_translate_firmware_enum_to_arg(struct pp_hwmgr *hwmgr,
return ret;
}
static enum cgs_ucode_id cz_convert_fw_type_to_cgs(uint32_t fw_type)
static enum cgs_ucode_id smu8_convert_fw_type_to_cgs(uint32_t fw_type)
{
enum cgs_ucode_id result = CGS_UCODE_ID_MAXIMUM;
@ -324,36 +324,36 @@ static enum cgs_ucode_id cz_convert_fw_type_to_cgs(uint32_t fw_type)
return result;
}
static int cz_smu_populate_single_scratch_task(
static int smu8_smu_populate_single_scratch_task(
struct pp_hwmgr *hwmgr,
enum cz_scratch_entry fw_enum,
enum smu8_scratch_entry fw_enum,
uint8_t type, bool is_last)
{
uint8_t i;
struct cz_smumgr *cz_smu = hwmgr->smu_backend;
struct TOC *toc = (struct TOC *)cz_smu->toc_buffer.kaddr;
struct SMU_Task *task = &toc->tasks[cz_smu->toc_entry_used_count++];
struct smu8_smumgr *smu8_smu = hwmgr->smu_backend;
struct TOC *toc = (struct TOC *)smu8_smu->toc_buffer.kaddr;
struct SMU_Task *task = &toc->tasks[smu8_smu->toc_entry_used_count++];
task->type = type;
task->arg = cz_translate_firmware_enum_to_arg(hwmgr, fw_enum);
task->next = is_last ? END_OF_TASK_LIST : cz_smu->toc_entry_used_count;
task->arg = smu8_translate_firmware_enum_to_arg(hwmgr, fw_enum);
task->next = is_last ? END_OF_TASK_LIST : smu8_smu->toc_entry_used_count;
for (i = 0; i < cz_smu->scratch_buffer_length; i++)
if (cz_smu->scratch_buffer[i].firmware_ID == fw_enum)
for (i = 0; i < smu8_smu->scratch_buffer_length; i++)
if (smu8_smu->scratch_buffer[i].firmware_ID == fw_enum)
break;
if (i >= cz_smu->scratch_buffer_length) {
if (i >= smu8_smu->scratch_buffer_length) {
pr_err("Invalid Firmware Type\n");
return -EINVAL;
}
task->addr.low = lower_32_bits(cz_smu->scratch_buffer[i].mc_addr);
task->addr.high = upper_32_bits(cz_smu->scratch_buffer[i].mc_addr);
task->size_bytes = cz_smu->scratch_buffer[i].data_size;
task->addr.low = lower_32_bits(smu8_smu->scratch_buffer[i].mc_addr);
task->addr.high = upper_32_bits(smu8_smu->scratch_buffer[i].mc_addr);
task->size_bytes = smu8_smu->scratch_buffer[i].data_size;
if (CZ_SCRATCH_ENTRY_DATA_ID_IH_REGISTERS == fw_enum) {
struct cz_ih_meta_data *pIHReg_restore =
(struct cz_ih_meta_data *)cz_smu->scratch_buffer[i].kaddr;
if (SMU8_SCRATCH_ENTRY_DATA_ID_IH_REGISTERS == fw_enum) {
struct smu8_ih_meta_data *pIHReg_restore =
(struct smu8_ih_meta_data *)smu8_smu->scratch_buffer[i].kaddr;
pIHReg_restore->command =
METADATA_CMD_MODE0 | METADATA_PERFORM_ON_LOAD;
}
@ -361,53 +361,53 @@ static int cz_smu_populate_single_scratch_task(
return 0;
}
static int cz_smu_populate_single_ucode_load_task(
static int smu8_smu_populate_single_ucode_load_task(
struct pp_hwmgr *hwmgr,
enum cz_scratch_entry fw_enum,
enum smu8_scratch_entry fw_enum,
bool is_last)
{
uint8_t i;
struct cz_smumgr *cz_smu = hwmgr->smu_backend;
struct TOC *toc = (struct TOC *)cz_smu->toc_buffer.kaddr;
struct SMU_Task *task = &toc->tasks[cz_smu->toc_entry_used_count++];
struct smu8_smumgr *smu8_smu = hwmgr->smu_backend;
struct TOC *toc = (struct TOC *)smu8_smu->toc_buffer.kaddr;
struct SMU_Task *task = &toc->tasks[smu8_smu->toc_entry_used_count++];
task->type = TASK_TYPE_UCODE_LOAD;
task->arg = cz_translate_firmware_enum_to_arg(hwmgr, fw_enum);
task->next = is_last ? END_OF_TASK_LIST : cz_smu->toc_entry_used_count;
task->arg = smu8_translate_firmware_enum_to_arg(hwmgr, fw_enum);
task->next = is_last ? END_OF_TASK_LIST : smu8_smu->toc_entry_used_count;
for (i = 0; i < cz_smu->driver_buffer_length; i++)
if (cz_smu->driver_buffer[i].firmware_ID == fw_enum)
for (i = 0; i < smu8_smu->driver_buffer_length; i++)
if (smu8_smu->driver_buffer[i].firmware_ID == fw_enum)
break;
if (i >= cz_smu->driver_buffer_length) {
if (i >= smu8_smu->driver_buffer_length) {
pr_err("Invalid Firmware Type\n");
return -EINVAL;
}
task->addr.low = lower_32_bits(cz_smu->driver_buffer[i].mc_addr);
task->addr.high = upper_32_bits(cz_smu->driver_buffer[i].mc_addr);
task->size_bytes = cz_smu->driver_buffer[i].data_size;
task->addr.low = lower_32_bits(smu8_smu->driver_buffer[i].mc_addr);
task->addr.high = upper_32_bits(smu8_smu->driver_buffer[i].mc_addr);
task->size_bytes = smu8_smu->driver_buffer[i].data_size;
return 0;
}
static int cz_smu_construct_toc_for_rlc_aram_save(struct pp_hwmgr *hwmgr)
static int smu8_smu_construct_toc_for_rlc_aram_save(struct pp_hwmgr *hwmgr)
{
struct cz_smumgr *cz_smu = hwmgr->smu_backend;
struct smu8_smumgr *smu8_smu = hwmgr->smu_backend;
cz_smu->toc_entry_aram = cz_smu->toc_entry_used_count;
cz_smu_populate_single_scratch_task(hwmgr,
CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_ARAM,
smu8_smu->toc_entry_aram = smu8_smu->toc_entry_used_count;
smu8_smu_populate_single_scratch_task(hwmgr,
SMU8_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_ARAM,
TASK_TYPE_UCODE_SAVE, true);
return 0;
}
static int cz_smu_initialize_toc_empty_job_list(struct pp_hwmgr *hwmgr)
static int smu8_smu_initialize_toc_empty_job_list(struct pp_hwmgr *hwmgr)
{
int i;
struct cz_smumgr *cz_smu = hwmgr->smu_backend;
struct TOC *toc = (struct TOC *)cz_smu->toc_buffer.kaddr;
struct smu8_smumgr *smu8_smu = hwmgr->smu_backend;
struct TOC *toc = (struct TOC *)smu8_smu->toc_buffer.kaddr;
for (i = 0; i < NUM_JOBLIST_ENTRIES; i++)
toc->JobList[i] = (uint8_t)IGNORE_JOB;
@ -415,248 +415,248 @@ static int cz_smu_initialize_toc_empty_job_list(struct pp_hwmgr *hwmgr)
return 0;
}
static int cz_smu_construct_toc_for_vddgfx_enter(struct pp_hwmgr *hwmgr)
static int smu8_smu_construct_toc_for_vddgfx_enter(struct pp_hwmgr *hwmgr)
{
struct cz_smumgr *cz_smu = hwmgr->smu_backend;
struct TOC *toc = (struct TOC *)cz_smu->toc_buffer.kaddr;
struct smu8_smumgr *smu8_smu = hwmgr->smu_backend;
struct TOC *toc = (struct TOC *)smu8_smu->toc_buffer.kaddr;
toc->JobList[JOB_GFX_SAVE] = (uint8_t)cz_smu->toc_entry_used_count;
cz_smu_populate_single_scratch_task(hwmgr,
CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SCRATCH,
toc->JobList[JOB_GFX_SAVE] = (uint8_t)smu8_smu->toc_entry_used_count;
smu8_smu_populate_single_scratch_task(hwmgr,
SMU8_SCRATCH_ENTRY_UCODE_ID_RLC_SCRATCH,
TASK_TYPE_UCODE_SAVE, false);
cz_smu_populate_single_scratch_task(hwmgr,
CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_DRAM,
smu8_smu_populate_single_scratch_task(hwmgr,
SMU8_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_DRAM,
TASK_TYPE_UCODE_SAVE, true);
return 0;
}
static int cz_smu_construct_toc_for_vddgfx_exit(struct pp_hwmgr *hwmgr)
static int smu8_smu_construct_toc_for_vddgfx_exit(struct pp_hwmgr *hwmgr)
{
struct cz_smumgr *cz_smu = hwmgr->smu_backend;
struct TOC *toc = (struct TOC *)cz_smu->toc_buffer.kaddr;
struct smu8_smumgr *smu8_smu = hwmgr->smu_backend;
struct TOC *toc = (struct TOC *)smu8_smu->toc_buffer.kaddr;
toc->JobList[JOB_GFX_RESTORE] = (uint8_t)cz_smu->toc_entry_used_count;
toc->JobList[JOB_GFX_RESTORE] = (uint8_t)smu8_smu->toc_entry_used_count;
cz_smu_populate_single_ucode_load_task(hwmgr,
CZ_SCRATCH_ENTRY_UCODE_ID_CP_CE, false);
cz_smu_populate_single_ucode_load_task(hwmgr,
CZ_SCRATCH_ENTRY_UCODE_ID_CP_PFP, false);
cz_smu_populate_single_ucode_load_task(hwmgr,
CZ_SCRATCH_ENTRY_UCODE_ID_CP_ME, false);
cz_smu_populate_single_ucode_load_task(hwmgr,
CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1, false);
smu8_smu_populate_single_ucode_load_task(hwmgr,
SMU8_SCRATCH_ENTRY_UCODE_ID_CP_CE, false);
smu8_smu_populate_single_ucode_load_task(hwmgr,
SMU8_SCRATCH_ENTRY_UCODE_ID_CP_PFP, false);
smu8_smu_populate_single_ucode_load_task(hwmgr,
SMU8_SCRATCH_ENTRY_UCODE_ID_CP_ME, false);
smu8_smu_populate_single_ucode_load_task(hwmgr,
SMU8_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1, false);
if (hwmgr->chip_id == CHIP_STONEY)
cz_smu_populate_single_ucode_load_task(hwmgr,
CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1, false);
smu8_smu_populate_single_ucode_load_task(hwmgr,
SMU8_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1, false);
else
cz_smu_populate_single_ucode_load_task(hwmgr,
CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT2, false);
smu8_smu_populate_single_ucode_load_task(hwmgr,
SMU8_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT2, false);
cz_smu_populate_single_ucode_load_task(hwmgr,
CZ_SCRATCH_ENTRY_UCODE_ID_RLC_G, false);
smu8_smu_populate_single_ucode_load_task(hwmgr,
SMU8_SCRATCH_ENTRY_UCODE_ID_RLC_G, false);
/* populate scratch */
cz_smu_populate_single_scratch_task(hwmgr,
CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SCRATCH,
smu8_smu_populate_single_scratch_task(hwmgr,
SMU8_SCRATCH_ENTRY_UCODE_ID_RLC_SCRATCH,
TASK_TYPE_UCODE_LOAD, false);
cz_smu_populate_single_scratch_task(hwmgr,
CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_ARAM,
smu8_smu_populate_single_scratch_task(hwmgr,
SMU8_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_ARAM,
TASK_TYPE_UCODE_LOAD, false);
cz_smu_populate_single_scratch_task(hwmgr,
CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_DRAM,
smu8_smu_populate_single_scratch_task(hwmgr,
SMU8_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_DRAM,
TASK_TYPE_UCODE_LOAD, true);
return 0;
}
static int cz_smu_construct_toc_for_power_profiling(struct pp_hwmgr *hwmgr)
static int smu8_smu_construct_toc_for_power_profiling(struct pp_hwmgr *hwmgr)
{
struct cz_smumgr *cz_smu = hwmgr->smu_backend;
struct smu8_smumgr *smu8_smu = hwmgr->smu_backend;
cz_smu->toc_entry_power_profiling_index = cz_smu->toc_entry_used_count;
smu8_smu->toc_entry_power_profiling_index = smu8_smu->toc_entry_used_count;
cz_smu_populate_single_scratch_task(hwmgr,
CZ_SCRATCH_ENTRY_UCODE_ID_POWER_PROFILING,
smu8_smu_populate_single_scratch_task(hwmgr,
SMU8_SCRATCH_ENTRY_UCODE_ID_POWER_PROFILING,
TASK_TYPE_INITIALIZE, true);
return 0;
}
static int cz_smu_construct_toc_for_bootup(struct pp_hwmgr *hwmgr)
static int smu8_smu_construct_toc_for_bootup(struct pp_hwmgr *hwmgr)
{
struct cz_smumgr *cz_smu = hwmgr->smu_backend;
struct smu8_smumgr *smu8_smu = hwmgr->smu_backend;
cz_smu->toc_entry_initialize_index = cz_smu->toc_entry_used_count;
smu8_smu->toc_entry_initialize_index = smu8_smu->toc_entry_used_count;
cz_smu_populate_single_ucode_load_task(hwmgr,
CZ_SCRATCH_ENTRY_UCODE_ID_SDMA0, false);
smu8_smu_populate_single_ucode_load_task(hwmgr,
SMU8_SCRATCH_ENTRY_UCODE_ID_SDMA0, false);
if (hwmgr->chip_id != CHIP_STONEY)
cz_smu_populate_single_ucode_load_task(hwmgr,
CZ_SCRATCH_ENTRY_UCODE_ID_SDMA1, false);
cz_smu_populate_single_ucode_load_task(hwmgr,
CZ_SCRATCH_ENTRY_UCODE_ID_CP_CE, false);
cz_smu_populate_single_ucode_load_task(hwmgr,
CZ_SCRATCH_ENTRY_UCODE_ID_CP_PFP, false);
cz_smu_populate_single_ucode_load_task(hwmgr,
CZ_SCRATCH_ENTRY_UCODE_ID_CP_ME, false);
cz_smu_populate_single_ucode_load_task(hwmgr,
CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1, false);
smu8_smu_populate_single_ucode_load_task(hwmgr,
SMU8_SCRATCH_ENTRY_UCODE_ID_SDMA1, false);
smu8_smu_populate_single_ucode_load_task(hwmgr,
SMU8_SCRATCH_ENTRY_UCODE_ID_CP_CE, false);
smu8_smu_populate_single_ucode_load_task(hwmgr,
SMU8_SCRATCH_ENTRY_UCODE_ID_CP_PFP, false);
smu8_smu_populate_single_ucode_load_task(hwmgr,
SMU8_SCRATCH_ENTRY_UCODE_ID_CP_ME, false);
smu8_smu_populate_single_ucode_load_task(hwmgr,
SMU8_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1, false);
if (hwmgr->chip_id != CHIP_STONEY)
cz_smu_populate_single_ucode_load_task(hwmgr,
CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT2, false);
cz_smu_populate_single_ucode_load_task(hwmgr,
CZ_SCRATCH_ENTRY_UCODE_ID_RLC_G, true);
smu8_smu_populate_single_ucode_load_task(hwmgr,
SMU8_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT2, false);
smu8_smu_populate_single_ucode_load_task(hwmgr,
SMU8_SCRATCH_ENTRY_UCODE_ID_RLC_G, true);
return 0;
}
static int cz_smu_construct_toc_for_clock_table(struct pp_hwmgr *hwmgr)
static int smu8_smu_construct_toc_for_clock_table(struct pp_hwmgr *hwmgr)
{
struct cz_smumgr *cz_smu = hwmgr->smu_backend;
struct smu8_smumgr *smu8_smu = hwmgr->smu_backend;
cz_smu->toc_entry_clock_table = cz_smu->toc_entry_used_count;
smu8_smu->toc_entry_clock_table = smu8_smu->toc_entry_used_count;
cz_smu_populate_single_scratch_task(hwmgr,
CZ_SCRATCH_ENTRY_SMU8_FUSION_CLKTABLE,
smu8_smu_populate_single_scratch_task(hwmgr,
SMU8_SCRATCH_ENTRY_SMU8_FUSION_CLKTABLE,
TASK_TYPE_INITIALIZE, true);
return 0;
}
static int cz_smu_construct_toc(struct pp_hwmgr *hwmgr)
static int smu8_smu_construct_toc(struct pp_hwmgr *hwmgr)
{
struct cz_smumgr *cz_smu = hwmgr->smu_backend;
struct smu8_smumgr *smu8_smu = hwmgr->smu_backend;
cz_smu->toc_entry_used_count = 0;
cz_smu_initialize_toc_empty_job_list(hwmgr);
cz_smu_construct_toc_for_rlc_aram_save(hwmgr);
cz_smu_construct_toc_for_vddgfx_enter(hwmgr);
cz_smu_construct_toc_for_vddgfx_exit(hwmgr);
cz_smu_construct_toc_for_power_profiling(hwmgr);
cz_smu_construct_toc_for_bootup(hwmgr);
cz_smu_construct_toc_for_clock_table(hwmgr);
smu8_smu->toc_entry_used_count = 0;
smu8_smu_initialize_toc_empty_job_list(hwmgr);
smu8_smu_construct_toc_for_rlc_aram_save(hwmgr);
smu8_smu_construct_toc_for_vddgfx_enter(hwmgr);
smu8_smu_construct_toc_for_vddgfx_exit(hwmgr);
smu8_smu_construct_toc_for_power_profiling(hwmgr);
smu8_smu_construct_toc_for_bootup(hwmgr);
smu8_smu_construct_toc_for_clock_table(hwmgr);
return 0;
}
static int cz_smu_populate_firmware_entries(struct pp_hwmgr *hwmgr)
static int smu8_smu_populate_firmware_entries(struct pp_hwmgr *hwmgr)
{
struct cz_smumgr *cz_smu = hwmgr->smu_backend;
struct smu8_smumgr *smu8_smu = hwmgr->smu_backend;
uint32_t firmware_type;
uint32_t i;
int ret;
enum cgs_ucode_id ucode_id;
struct cgs_firmware_info info = {0};
cz_smu->driver_buffer_length = 0;
smu8_smu->driver_buffer_length = 0;
for (i = 0; i < ARRAY_SIZE(firmware_list); i++) {
firmware_type = cz_translate_firmware_enum_to_arg(hwmgr,
firmware_type = smu8_translate_firmware_enum_to_arg(hwmgr,
firmware_list[i]);
ucode_id = cz_convert_fw_type_to_cgs(firmware_type);
ucode_id = smu8_convert_fw_type_to_cgs(firmware_type);
ret = cgs_get_firmware_info(hwmgr->device,
ucode_id, &info);
if (ret == 0) {
cz_smu->driver_buffer[i].mc_addr = info.mc_addr;
smu8_smu->driver_buffer[i].mc_addr = info.mc_addr;
cz_smu->driver_buffer[i].data_size = info.image_size;
smu8_smu->driver_buffer[i].data_size = info.image_size;
cz_smu->driver_buffer[i].firmware_ID = firmware_list[i];
cz_smu->driver_buffer_length++;
smu8_smu->driver_buffer[i].firmware_ID = firmware_list[i];
smu8_smu->driver_buffer_length++;
}
}
return 0;
}
static int cz_smu_populate_single_scratch_entry(
static int smu8_smu_populate_single_scratch_entry(
struct pp_hwmgr *hwmgr,
enum cz_scratch_entry scratch_type,
enum smu8_scratch_entry scratch_type,
uint32_t ulsize_byte,
struct cz_buffer_entry *entry)
struct smu8_buffer_entry *entry)
{
struct cz_smumgr *cz_smu = hwmgr->smu_backend;
struct smu8_smumgr *smu8_smu = hwmgr->smu_backend;
uint32_t ulsize_aligned = SIZE_ALIGN_32(ulsize_byte);
entry->data_size = ulsize_byte;
entry->kaddr = (char *) cz_smu->smu_buffer.kaddr +
cz_smu->smu_buffer_used_bytes;
entry->mc_addr = cz_smu->smu_buffer.mc_addr + cz_smu->smu_buffer_used_bytes;
entry->kaddr = (char *) smu8_smu->smu_buffer.kaddr +
smu8_smu->smu_buffer_used_bytes;
entry->mc_addr = smu8_smu->smu_buffer.mc_addr + smu8_smu->smu_buffer_used_bytes;
entry->firmware_ID = scratch_type;
cz_smu->smu_buffer_used_bytes += ulsize_aligned;
smu8_smu->smu_buffer_used_bytes += ulsize_aligned;
return 0;
}
static int cz_download_pptable_settings(struct pp_hwmgr *hwmgr, void **table)
static int smu8_download_pptable_settings(struct pp_hwmgr *hwmgr, void **table)
{
struct cz_smumgr *cz_smu = hwmgr->smu_backend;
struct smu8_smumgr *smu8_smu = hwmgr->smu_backend;
unsigned long i;
for (i = 0; i < cz_smu->scratch_buffer_length; i++) {
if (cz_smu->scratch_buffer[i].firmware_ID
== CZ_SCRATCH_ENTRY_SMU8_FUSION_CLKTABLE)
for (i = 0; i < smu8_smu->scratch_buffer_length; i++) {
if (smu8_smu->scratch_buffer[i].firmware_ID
== SMU8_SCRATCH_ENTRY_SMU8_FUSION_CLKTABLE)
break;
}
*table = (struct SMU8_Fusion_ClkTable *)cz_smu->scratch_buffer[i].kaddr;
*table = (struct SMU8_Fusion_ClkTable *)smu8_smu->scratch_buffer[i].kaddr;
cz_send_msg_to_smc_with_parameter(hwmgr,
smu8_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetClkTableAddrHi,
upper_32_bits(cz_smu->scratch_buffer[i].mc_addr));
upper_32_bits(smu8_smu->scratch_buffer[i].mc_addr));
cz_send_msg_to_smc_with_parameter(hwmgr,
smu8_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetClkTableAddrLo,
lower_32_bits(cz_smu->scratch_buffer[i].mc_addr));
lower_32_bits(smu8_smu->scratch_buffer[i].mc_addr));
cz_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_ExecuteJob,
cz_smu->toc_entry_clock_table);
smu8_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_ExecuteJob,
smu8_smu->toc_entry_clock_table);
cz_send_msg_to_smc(hwmgr, PPSMC_MSG_ClkTableXferToDram);
smu8_send_msg_to_smc(hwmgr, PPSMC_MSG_ClkTableXferToDram);
return 0;
}
static int cz_upload_pptable_settings(struct pp_hwmgr *hwmgr)
static int smu8_upload_pptable_settings(struct pp_hwmgr *hwmgr)
{
struct cz_smumgr *cz_smu = hwmgr->smu_backend;
struct smu8_smumgr *smu8_smu = hwmgr->smu_backend;
unsigned long i;
for (i = 0; i < cz_smu->scratch_buffer_length; i++) {
if (cz_smu->scratch_buffer[i].firmware_ID
== CZ_SCRATCH_ENTRY_SMU8_FUSION_CLKTABLE)
for (i = 0; i < smu8_smu->scratch_buffer_length; i++) {
if (smu8_smu->scratch_buffer[i].firmware_ID
== SMU8_SCRATCH_ENTRY_SMU8_FUSION_CLKTABLE)
break;
}
cz_send_msg_to_smc_with_parameter(hwmgr,
smu8_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetClkTableAddrHi,
upper_32_bits(cz_smu->scratch_buffer[i].mc_addr));
upper_32_bits(smu8_smu->scratch_buffer[i].mc_addr));
cz_send_msg_to_smc_with_parameter(hwmgr,
smu8_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetClkTableAddrLo,
lower_32_bits(cz_smu->scratch_buffer[i].mc_addr));
lower_32_bits(smu8_smu->scratch_buffer[i].mc_addr));
cz_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_ExecuteJob,
cz_smu->toc_entry_clock_table);
smu8_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_ExecuteJob,
smu8_smu->toc_entry_clock_table);
cz_send_msg_to_smc(hwmgr, PPSMC_MSG_ClkTableXferToSmu);
smu8_send_msg_to_smc(hwmgr, PPSMC_MSG_ClkTableXferToSmu);
return 0;
}
static int cz_request_smu_load_fw(struct pp_hwmgr *hwmgr)
static int smu8_request_smu_load_fw(struct pp_hwmgr *hwmgr)
{
struct cz_smumgr *cz_smu = hwmgr->smu_backend;
struct smu8_smumgr *smu8_smu = hwmgr->smu_backend;
uint32_t smc_address;
if (!hwmgr->reload_fw) {
@ -664,37 +664,37 @@ static int cz_request_smu_load_fw(struct pp_hwmgr *hwmgr)
return 0;
}
cz_smu_populate_firmware_entries(hwmgr);
smu8_smu_populate_firmware_entries(hwmgr);
cz_smu_construct_toc(hwmgr);
smu8_smu_construct_toc(hwmgr);
smc_address = SMU8_FIRMWARE_HEADER_LOCATION +
offsetof(struct SMU8_Firmware_Header, UcodeLoadStatus);
cz_write_smc_sram_dword(hwmgr, smc_address, 0, smc_address+4);
smu8_write_smc_sram_dword(hwmgr, smc_address, 0, smc_address+4);
cz_send_msg_to_smc_with_parameter(hwmgr,
smu8_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_DriverDramAddrHi,
upper_32_bits(cz_smu->toc_buffer.mc_addr));
upper_32_bits(smu8_smu->toc_buffer.mc_addr));
cz_send_msg_to_smc_with_parameter(hwmgr,
smu8_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_DriverDramAddrLo,
lower_32_bits(cz_smu->toc_buffer.mc_addr));
lower_32_bits(smu8_smu->toc_buffer.mc_addr));
cz_send_msg_to_smc(hwmgr, PPSMC_MSG_InitJobs);
smu8_send_msg_to_smc(hwmgr, PPSMC_MSG_InitJobs);
cz_send_msg_to_smc_with_parameter(hwmgr,
smu8_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_ExecuteJob,
cz_smu->toc_entry_aram);
cz_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_ExecuteJob,
cz_smu->toc_entry_power_profiling_index);
smu8_smu->toc_entry_aram);
smu8_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_ExecuteJob,
smu8_smu->toc_entry_power_profiling_index);
return cz_send_msg_to_smc_with_parameter(hwmgr,
return smu8_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_ExecuteJob,
cz_smu->toc_entry_initialize_index);
smu8_smu->toc_entry_initialize_index);
}
static int cz_start_smu(struct pp_hwmgr *hwmgr)
static int smu8_start_smu(struct pp_hwmgr *hwmgr)
{
int ret = 0;
uint32_t fw_to_check = 0;
@ -724,32 +724,32 @@ static int cz_start_smu(struct pp_hwmgr *hwmgr)
if (hwmgr->chip_id == CHIP_STONEY)
fw_to_check &= ~(UCODE_ID_SDMA1_MASK | UCODE_ID_CP_MEC_JT2_MASK);
ret = cz_request_smu_load_fw(hwmgr);
ret = smu8_request_smu_load_fw(hwmgr);
if (ret)
pr_err("SMU firmware load failed\n");
cz_check_fw_load_finish(hwmgr, fw_to_check);
smu8_check_fw_load_finish(hwmgr, fw_to_check);
ret = cz_load_mec_firmware(hwmgr);
ret = smu8_load_mec_firmware(hwmgr);
if (ret)
pr_err("Mec Firmware load failed\n");
return ret;
}
static int cz_smu_init(struct pp_hwmgr *hwmgr)
static int smu8_smu_init(struct pp_hwmgr *hwmgr)
{
int ret = 0;
struct cz_smumgr *cz_smu;
struct smu8_smumgr *smu8_smu;
cz_smu = kzalloc(sizeof(struct cz_smumgr), GFP_KERNEL);
if (cz_smu == NULL)
smu8_smu = kzalloc(sizeof(struct smu8_smumgr), GFP_KERNEL);
if (smu8_smu == NULL)
return -ENOMEM;
hwmgr->smu_backend = cz_smu;
hwmgr->smu_backend = smu8_smu;
cz_smu->toc_buffer.data_size = 4096;
cz_smu->smu_buffer.data_size =
smu8_smu->toc_buffer.data_size = 4096;
smu8_smu->smu_buffer.data_size =
ALIGN(UCODE_ID_RLC_SCRATCH_SIZE_BYTE, 32) +
ALIGN(UCODE_ID_RLC_SRM_ARAM_SIZE_BYTE, 32) +
ALIGN(UCODE_ID_RLC_SRM_DRAM_SIZE_BYTE, 32) +
@ -757,60 +757,60 @@ static int cz_smu_init(struct pp_hwmgr *hwmgr)
ALIGN(sizeof(struct SMU8_Fusion_ClkTable), 32);
ret = amdgpu_bo_create_kernel((struct amdgpu_device *)hwmgr->adev,
cz_smu->toc_buffer.data_size,
smu8_smu->toc_buffer.data_size,
PAGE_SIZE,
AMDGPU_GEM_DOMAIN_VRAM,
&cz_smu->toc_buffer.handle,
&cz_smu->toc_buffer.mc_addr,
&cz_smu->toc_buffer.kaddr);
&smu8_smu->toc_buffer.handle,
&smu8_smu->toc_buffer.mc_addr,
&smu8_smu->toc_buffer.kaddr);
if (ret)
goto err2;
ret = amdgpu_bo_create_kernel((struct amdgpu_device *)hwmgr->adev,
cz_smu->smu_buffer.data_size,
smu8_smu->smu_buffer.data_size,
PAGE_SIZE,
AMDGPU_GEM_DOMAIN_VRAM,
&cz_smu->smu_buffer.handle,
&cz_smu->smu_buffer.mc_addr,
&cz_smu->smu_buffer.kaddr);
&smu8_smu->smu_buffer.handle,
&smu8_smu->smu_buffer.mc_addr,
&smu8_smu->smu_buffer.kaddr);
if (ret)
goto err1;
if (0 != cz_smu_populate_single_scratch_entry(hwmgr,
CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SCRATCH,
if (0 != smu8_smu_populate_single_scratch_entry(hwmgr,
SMU8_SCRATCH_ENTRY_UCODE_ID_RLC_SCRATCH,
UCODE_ID_RLC_SCRATCH_SIZE_BYTE,
&cz_smu->scratch_buffer[cz_smu->scratch_buffer_length++])) {
&smu8_smu->scratch_buffer[smu8_smu->scratch_buffer_length++])) {
pr_err("Error when Populate Firmware Entry.\n");
goto err0;
}
if (0 != cz_smu_populate_single_scratch_entry(hwmgr,
CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_ARAM,
if (0 != smu8_smu_populate_single_scratch_entry(hwmgr,
SMU8_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_ARAM,
UCODE_ID_RLC_SRM_ARAM_SIZE_BYTE,
&cz_smu->scratch_buffer[cz_smu->scratch_buffer_length++])) {
&smu8_smu->scratch_buffer[smu8_smu->scratch_buffer_length++])) {
pr_err("Error when Populate Firmware Entry.\n");
goto err0;
}
if (0 != cz_smu_populate_single_scratch_entry(hwmgr,
CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_DRAM,
if (0 != smu8_smu_populate_single_scratch_entry(hwmgr,
SMU8_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_DRAM,
UCODE_ID_RLC_SRM_DRAM_SIZE_BYTE,
&cz_smu->scratch_buffer[cz_smu->scratch_buffer_length++])) {
&smu8_smu->scratch_buffer[smu8_smu->scratch_buffer_length++])) {
pr_err("Error when Populate Firmware Entry.\n");
goto err0;
}
if (0 != cz_smu_populate_single_scratch_entry(hwmgr,
CZ_SCRATCH_ENTRY_UCODE_ID_POWER_PROFILING,
if (0 != smu8_smu_populate_single_scratch_entry(hwmgr,
SMU8_SCRATCH_ENTRY_UCODE_ID_POWER_PROFILING,
sizeof(struct SMU8_MultimediaPowerLogData),
&cz_smu->scratch_buffer[cz_smu->scratch_buffer_length++])) {
&smu8_smu->scratch_buffer[smu8_smu->scratch_buffer_length++])) {
pr_err("Error when Populate Firmware Entry.\n");
goto err0;
}
if (0 != cz_smu_populate_single_scratch_entry(hwmgr,
CZ_SCRATCH_ENTRY_SMU8_FUSION_CLKTABLE,
if (0 != smu8_smu_populate_single_scratch_entry(hwmgr,
SMU8_SCRATCH_ENTRY_SMU8_FUSION_CLKTABLE,
sizeof(struct SMU8_Fusion_ClkTable),
&cz_smu->scratch_buffer[cz_smu->scratch_buffer_length++])) {
&smu8_smu->scratch_buffer[smu8_smu->scratch_buffer_length++])) {
pr_err("Error when Populate Firmware Entry.\n");
goto err0;
}
@ -818,46 +818,46 @@ static int cz_smu_init(struct pp_hwmgr *hwmgr)
return 0;
err0:
amdgpu_bo_free_kernel(&cz_smu->smu_buffer.handle,
&cz_smu->smu_buffer.mc_addr,
&cz_smu->smu_buffer.kaddr);
amdgpu_bo_free_kernel(&smu8_smu->smu_buffer.handle,
&smu8_smu->smu_buffer.mc_addr,
&smu8_smu->smu_buffer.kaddr);
err1:
amdgpu_bo_free_kernel(&cz_smu->toc_buffer.handle,
&cz_smu->toc_buffer.mc_addr,
&cz_smu->toc_buffer.kaddr);
amdgpu_bo_free_kernel(&smu8_smu->toc_buffer.handle,
&smu8_smu->toc_buffer.mc_addr,
&smu8_smu->toc_buffer.kaddr);
err2:
kfree(cz_smu);
kfree(smu8_smu);
return -EINVAL;
}
static int cz_smu_fini(struct pp_hwmgr *hwmgr)
static int smu8_smu_fini(struct pp_hwmgr *hwmgr)
{
struct cz_smumgr *cz_smu;
struct smu8_smumgr *smu8_smu;
if (hwmgr == NULL || hwmgr->device == NULL)
return -EINVAL;
cz_smu = hwmgr->smu_backend;
if (cz_smu) {
amdgpu_bo_free_kernel(&cz_smu->toc_buffer.handle,
&cz_smu->toc_buffer.mc_addr,
&cz_smu->toc_buffer.kaddr);
amdgpu_bo_free_kernel(&cz_smu->smu_buffer.handle,
&cz_smu->smu_buffer.mc_addr,
&cz_smu->smu_buffer.kaddr);
kfree(cz_smu);
smu8_smu = hwmgr->smu_backend;
if (smu8_smu) {
amdgpu_bo_free_kernel(&smu8_smu->toc_buffer.handle,
&smu8_smu->toc_buffer.mc_addr,
&smu8_smu->toc_buffer.kaddr);
amdgpu_bo_free_kernel(&smu8_smu->smu_buffer.handle,
&smu8_smu->smu_buffer.mc_addr,
&smu8_smu->smu_buffer.kaddr);
kfree(smu8_smu);
}
return 0;
}
static bool cz_dpm_check_smu_features(struct pp_hwmgr *hwmgr,
static bool smu8_dpm_check_smu_features(struct pp_hwmgr *hwmgr,
unsigned long check_feature)
{
int result;
unsigned long features;
result = cz_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetFeatureStatus, 0);
result = smu8_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetFeatureStatus, 0);
if (result == 0) {
features = smum_get_argument(hwmgr);
if (features & check_feature)
@ -867,25 +867,25 @@ static bool cz_dpm_check_smu_features(struct pp_hwmgr *hwmgr,
return false;
}
static bool cz_is_dpm_running(struct pp_hwmgr *hwmgr)
static bool smu8_is_dpm_running(struct pp_hwmgr *hwmgr)
{
if (cz_dpm_check_smu_features(hwmgr, SMU_EnabledFeatureScoreboard_SclkDpmOn))
if (smu8_dpm_check_smu_features(hwmgr, SMU_EnabledFeatureScoreboard_SclkDpmOn))
return true;
return false;
}
const struct pp_smumgr_func cz_smu_funcs = {
.smu_init = cz_smu_init,
.smu_fini = cz_smu_fini,
.start_smu = cz_start_smu,
.check_fw_load_finish = cz_check_fw_load_finish,
const struct pp_smumgr_func smu8_smu_funcs = {
.smu_init = smu8_smu_init,
.smu_fini = smu8_smu_fini,
.start_smu = smu8_start_smu,
.check_fw_load_finish = smu8_check_fw_load_finish,
.request_smu_load_fw = NULL,
.request_smu_load_specific_fw = NULL,
.get_argument = cz_smum_get_argument,
.send_msg_to_smc = cz_send_msg_to_smc,
.send_msg_to_smc_with_parameter = cz_send_msg_to_smc_with_parameter,
.download_pptable_settings = cz_download_pptable_settings,
.upload_pptable_settings = cz_upload_pptable_settings,
.is_dpm_running = cz_is_dpm_running,
.get_argument = smu8_smum_get_argument,
.send_msg_to_smc = smu8_send_msg_to_smc,
.send_msg_to_smc_with_parameter = smu8_send_msg_to_smc_with_parameter,
.download_pptable_settings = smu8_download_pptable_settings,
.upload_pptable_settings = smu8_upload_pptable_settings,
.is_dpm_running = smu8_is_dpm_running,
};

82
drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.h
View File

@ -20,63 +20,63 @@
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef _CZ_SMUMGR_H_
#define _CZ_SMUMGR_H_
#ifndef _SMU8_SMUMGR_H_
#define _SMU8_SMUMGR_H_
#define MAX_NUM_FIRMWARE 8
#define MAX_NUM_SCRATCH 11
#define CZ_SCRATCH_SIZE_NONGFX_CLOCKGATING 1024
#define CZ_SCRATCH_SIZE_NONGFX_GOLDENSETTING 2048
#define CZ_SCRATCH_SIZE_SDMA_METADATA 1024
#define CZ_SCRATCH_SIZE_IH ((2*256+1)*4)
#define SMU8_SCRATCH_SIZE_NONGFX_CLOCKGATING 1024
#define SMU8_SCRATCH_SIZE_NONGFX_GOLDENSETTING 2048
#define SMU8_SCRATCH_SIZE_SDMA_METADATA 1024
#define SMU8_SCRATCH_SIZE_IH ((2*256+1)*4)
#define SMU_EnabledFeatureScoreboard_SclkDpmOn 0x00200000
enum cz_scratch_entry {
CZ_SCRATCH_ENTRY_UCODE_ID_SDMA0 = 0,
CZ_SCRATCH_ENTRY_UCODE_ID_SDMA1,
CZ_SCRATCH_ENTRY_UCODE_ID_CP_CE,
CZ_SCRATCH_ENTRY_UCODE_ID_CP_PFP,
CZ_SCRATCH_ENTRY_UCODE_ID_CP_ME,
CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1,
CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT2,
CZ_SCRATCH_ENTRY_UCODE_ID_GMCON_RENG,
CZ_SCRATCH_ENTRY_UCODE_ID_RLC_G,
CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SCRATCH,
CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_ARAM,
CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_DRAM,
CZ_SCRATCH_ENTRY_UCODE_ID_DMCU_ERAM,
CZ_SCRATCH_ENTRY_UCODE_ID_DMCU_IRAM,
CZ_SCRATCH_ENTRY_UCODE_ID_POWER_PROFILING,
CZ_SCRATCH_ENTRY_DATA_ID_SDMA_HALT,
CZ_SCRATCH_ENTRY_DATA_ID_SYS_CLOCKGATING,
CZ_SCRATCH_ENTRY_DATA_ID_SDMA_RING_REGS,
CZ_SCRATCH_ENTRY_DATA_ID_NONGFX_REINIT,
CZ_SCRATCH_ENTRY_DATA_ID_SDMA_START,
CZ_SCRATCH_ENTRY_DATA_ID_IH_REGISTERS,
CZ_SCRATCH_ENTRY_SMU8_FUSION_CLKTABLE
enum smu8_scratch_entry {
SMU8_SCRATCH_ENTRY_UCODE_ID_SDMA0 = 0,
SMU8_SCRATCH_ENTRY_UCODE_ID_SDMA1,
SMU8_SCRATCH_ENTRY_UCODE_ID_CP_CE,
SMU8_SCRATCH_ENTRY_UCODE_ID_CP_PFP,
SMU8_SCRATCH_ENTRY_UCODE_ID_CP_ME,
SMU8_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1,
SMU8_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT2,
SMU8_SCRATCH_ENTRY_UCODE_ID_GMCON_RENG,
SMU8_SCRATCH_ENTRY_UCODE_ID_RLC_G,
SMU8_SCRATCH_ENTRY_UCODE_ID_RLC_SCRATCH,
SMU8_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_ARAM,
SMU8_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_DRAM,
SMU8_SCRATCH_ENTRY_UCODE_ID_DMCU_ERAM,
SMU8_SCRATCH_ENTRY_UCODE_ID_DMCU_IRAM,
SMU8_SCRATCH_ENTRY_UCODE_ID_POWER_PROFILING,
SMU8_SCRATCH_ENTRY_DATA_ID_SDMA_HALT,
SMU8_SCRATCH_ENTRY_DATA_ID_SYS_CLOCKGATING,
SMU8_SCRATCH_ENTRY_DATA_ID_SDMA_RING_REGS,
SMU8_SCRATCH_ENTRY_DATA_ID_NONGFX_REINIT,
SMU8_SCRATCH_ENTRY_DATA_ID_SDMA_START,
SMU8_SCRATCH_ENTRY_DATA_ID_IH_REGISTERS,
SMU8_SCRATCH_ENTRY_SMU8_FUSION_CLKTABLE
};
struct cz_buffer_entry {
struct smu8_buffer_entry {
uint32_t data_size;
uint64_t mc_addr;
void *kaddr;
enum cz_scratch_entry firmware_ID;
enum smu8_scratch_entry firmware_ID;
struct amdgpu_bo *handle; /* as bo handle used when release bo */
};
struct cz_register_index_data_pair {
struct smu8_register_index_data_pair {
uint32_t offset;
uint32_t value;
};
struct cz_ih_meta_data {
struct smu8_ih_meta_data {
uint32_t command;
struct cz_register_index_data_pair register_index_value_pair[1];
struct smu8_register_index_data_pair register_index_value_pair[1];
};
struct cz_smumgr {
struct smu8_smumgr {
uint8_t driver_buffer_length;
uint8_t scratch_buffer_length;
uint16_t toc_entry_used_count;
@ -88,12 +88,12 @@ struct cz_smumgr {
uint16_t ih_register_restore_task_size;
uint16_t smu_buffer_used_bytes;
struct cz_buffer_entry toc_buffer;
struct cz_buffer_entry smu_buffer;
struct cz_buffer_entry firmware_buffer;
struct cz_buffer_entry driver_buffer[MAX_NUM_FIRMWARE];
struct cz_buffer_entry meta_data_buffer[MAX_NUM_FIRMWARE];
struct cz_buffer_entry scratch_buffer[MAX_NUM_SCRATCH];
struct smu8_buffer_entry toc_buffer;
struct smu8_buffer_entry smu_buffer;
struct smu8_buffer_entry firmware_buffer;
struct smu8_buffer_entry driver_buffer[MAX_NUM_FIRMWARE];
struct smu8_buffer_entry meta_data_buffer[MAX_NUM_FIRMWARE];
struct smu8_buffer_entry scratch_buffer[MAX_NUM_SCRATCH];
};
#endif