x86/fpu: Clean up asm/fpu/types.h
- add header guards - standardize vertical alignment - add comments about MPX No code changed. Reviewed-by: Borislav Petkov <bp@alien8.de> Cc: Andy Lutomirski <luto@amacapital.net> Cc: Dave Hansen <dave.hansen@linux.intel.com> Cc: Fenghua Yu <fenghua.yu@intel.com> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Oleg Nesterov <oleg@redhat.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Ingo Molnar <mingo@kernel.org>
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@ -1,3 +1,8 @@
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/*
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* FPU data structures:
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*/
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#ifndef _ASM_X86_FPU_H
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#define _ASM_X86_FPU_H
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#define MXCSR_DEFAULT 0x1f80
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#define MXCSR_DEFAULT 0x1f80
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@ -52,6 +57,9 @@ struct i387_fxsave_struct {
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} __attribute__((aligned(16)));
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} __attribute__((aligned(16)));
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/*
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* Software based FPU emulation state:
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*/
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struct i387_soft_struct {
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struct i387_soft_struct {
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u32 cwd;
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u32 cwd;
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u32 swd;
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u32 swd;
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@ -74,38 +82,39 @@ struct i387_soft_struct {
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struct ymmh_struct {
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struct ymmh_struct {
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/* 16 * 16 bytes for each YMMH-reg = 256 bytes */
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/* 16 * 16 bytes for each YMMH-reg = 256 bytes */
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u32 ymmh_space[64];
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u32 ymmh_space[64];
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};
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};
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/* We don't support LWP yet: */
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/* We don't support LWP yet: */
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struct lwp_struct {
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struct lwp_struct {
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u8 reserved[128];
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u8 reserved[128];
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};
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};
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/* Intel MPX support: */
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struct bndreg {
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struct bndreg {
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u64 lower_bound;
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u64 lower_bound;
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u64 upper_bound;
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u64 upper_bound;
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} __packed;
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} __packed;
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struct bndcsr {
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struct bndcsr {
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u64 bndcfgu;
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u64 bndcfgu;
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u64 bndstatus;
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u64 bndstatus;
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} __packed;
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} __packed;
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struct xsave_hdr_struct {
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struct xsave_hdr_struct {
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u64 xstate_bv;
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u64 xstate_bv;
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u64 xcomp_bv;
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u64 xcomp_bv;
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u64 reserved[6];
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u64 reserved[6];
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} __attribute__((packed));
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} __attribute__((packed));
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struct xsave_struct {
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struct xsave_struct {
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struct i387_fxsave_struct i387;
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struct i387_fxsave_struct i387;
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struct xsave_hdr_struct xsave_hdr;
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struct xsave_hdr_struct xsave_hdr;
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struct ymmh_struct ymmh;
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struct ymmh_struct ymmh;
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struct lwp_struct lwp;
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struct lwp_struct lwp;
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struct bndreg bndreg[4];
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struct bndreg bndreg[4];
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struct bndcsr bndcsr;
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struct bndcsr bndcsr;
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/* new processor state extensions will go here */
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/* New processor state extensions will go here. */
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} __attribute__ ((packed, aligned (64)));
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} __attribute__ ((packed, aligned (64)));
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union thread_xstate {
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union thread_xstate {
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@ -116,9 +125,9 @@ union thread_xstate {
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};
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};
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struct fpu {
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struct fpu {
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unsigned int last_cpu;
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unsigned int last_cpu;
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unsigned int has_fpu;
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unsigned int has_fpu;
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union thread_xstate *state;
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union thread_xstate *state;
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/*
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/*
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* This counter contains the number of consecutive context switches
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* This counter contains the number of consecutive context switches
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* during which the FPU stays used. If this is over a threshold, the
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* during which the FPU stays used. If this is over a threshold, the
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@ -127,6 +136,7 @@ struct fpu {
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* wraps and the context switch behavior turns lazy again; this is to
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* wraps and the context switch behavior turns lazy again; this is to
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* deal with bursty apps that only use the FPU for a short time:
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* deal with bursty apps that only use the FPU for a short time:
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*/
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*/
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unsigned char counter;
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unsigned char counter;
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};
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};
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#endif /* _ASM_X86_FPU_H */
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