ARM: OMAP2+: tusb6010: generic timing calculation
Generic gpmc timing calculation helper is available now, use it instead of custom timing calculation. Signed-off-by: Afzal Mohammed <afzal@ti.com>
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Afzal Mohammed
parent
ac2d9ae194
commit
47acde1672
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@ -27,182 +27,88 @@ static u8 async_cs, sync_cs;
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static unsigned refclk_psec;
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/* t2_ps, when quantized to fclk units, must happen no earlier than
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* the clock after after t1_NS.
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*
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* Return a possibly updated value of t2_ps, converted to nsec.
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*/
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static unsigned
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next_clk(unsigned t1_NS, unsigned t2_ps, unsigned fclk_ps)
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{
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unsigned t1_ps = t1_NS * 1000;
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unsigned t1_f, t2_f;
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if ((t1_ps + fclk_ps) < t2_ps)
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return t2_ps / 1000;
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t1_f = (t1_ps + fclk_ps - 1) / fclk_ps;
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t2_f = (t2_ps + fclk_ps - 1) / fclk_ps;
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if (t1_f >= t2_f)
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t2_f = t1_f + 1;
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return (t2_f * fclk_ps) / 1000;
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}
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/* NOTE: timings are from tusb 6010 datasheet Rev 1.8, 12-Sept 2006 */
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static int tusb_set_async_mode(unsigned sysclk_ps, unsigned fclk_ps)
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static int tusb_set_async_mode(unsigned sysclk_ps)
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{
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struct gpmc_device_timings dev_t;
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struct gpmc_timings t;
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unsigned t_acsnh_advnh = sysclk_ps + 3000;
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unsigned tmp;
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memset(&t, 0, sizeof(t));
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memset(&dev_t, 0, sizeof(dev_t));
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/* CS_ON = t_acsnh_acsnl */
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t.cs_on = 8;
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/* ADV_ON = t_acsnh_advnh - t_advn */
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t.adv_on = next_clk(t.cs_on, t_acsnh_advnh - 7000, fclk_ps);
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dev_t.mux = true;
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/*
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* READ ... from omap2420 TRM fig 12-13
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*/
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dev_t.t_ceasu = 8 * 1000;
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dev_t.t_avdasu = t_acsnh_advnh - 7000;
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dev_t.t_ce_avd = 1000;
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dev_t.t_avdp_r = t_acsnh_advnh;
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dev_t.t_oeasu = t_acsnh_advnh + 1000;
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dev_t.t_oe = 300;
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dev_t.t_cez_r = 7000;
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dev_t.t_cez_w = dev_t.t_cez_r;
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dev_t.t_avdp_w = t_acsnh_advnh;
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dev_t.t_weasu = t_acsnh_advnh + 1000;
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dev_t.t_wpl = 300;
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dev_t.cyc_aavdh_we = 1;
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/* ADV_RD_OFF = t_acsnh_advnh */
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t.adv_rd_off = next_clk(t.adv_on, t_acsnh_advnh, fclk_ps);
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/* OE_ON = t_acsnh_advnh + t_advn_oen (then wait for nRDY) */
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t.oe_on = next_clk(t.adv_on, t_acsnh_advnh + 1000, fclk_ps);
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/* ACCESS = counters continue only after nRDY */
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tmp = t.oe_on * 1000 + 300;
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t.access = next_clk(t.oe_on, tmp, fclk_ps);
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/* OE_OFF = after data gets sampled */
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tmp = t.access * 1000;
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t.oe_off = next_clk(t.access, tmp, fclk_ps);
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t.cs_rd_off = t.oe_off;
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tmp = t.cs_rd_off * 1000 + 7000 /* t_acsn_rdy_z */;
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t.rd_cycle = next_clk(t.cs_rd_off, tmp, fclk_ps);
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/*
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* WRITE ... from omap2420 TRM fig 12-15
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*/
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/* ADV_WR_OFF = t_acsnh_advnh */
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t.adv_wr_off = t.adv_rd_off;
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/* WE_ON = t_acsnh_advnh + t_advn_wen (then wait for nRDY) */
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t.we_on = next_clk(t.adv_wr_off, t_acsnh_advnh + 1000, fclk_ps);
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/* WE_OFF = after data gets sampled */
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tmp = t.we_on * 1000 + 300;
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t.we_off = next_clk(t.we_on, tmp, fclk_ps);
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t.cs_wr_off = t.we_off;
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tmp = t.cs_wr_off * 1000 + 7000 /* t_acsn_rdy_z */;
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t.wr_cycle = next_clk(t.cs_wr_off, tmp, fclk_ps);
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gpmc_calc_timings(&t, &dev_t);
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return gpmc_cs_set_timings(async_cs, &t);
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}
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static int tusb_set_sync_mode(unsigned sysclk_ps, unsigned fclk_ps)
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static int tusb_set_sync_mode(unsigned sysclk_ps)
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{
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struct gpmc_device_timings dev_t;
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struct gpmc_timings t;
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unsigned t_scsnh_advnh = sysclk_ps + 3000;
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unsigned tmp;
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memset(&t, 0, sizeof(t));
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t.cs_on = 8;
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memset(&dev_t, 0, sizeof(dev_t));
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/* ADV_ON = t_acsnh_advnh - t_advn */
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t.adv_on = next_clk(t.cs_on, t_scsnh_advnh - 7000, fclk_ps);
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dev_t.mux = true;
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dev_t.sync_read = true;
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dev_t.sync_write = true;
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/* GPMC_CLK rate = fclk rate / div */
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t.sync_clk = 11100 /* 11.1 nsec */;
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tmp = (t.sync_clk + fclk_ps - 1) / fclk_ps;
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if (tmp > 4)
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return -ERANGE;
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if (tmp == 0)
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tmp = 1;
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t.page_burst_access = (fclk_ps * tmp) / 1000;
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dev_t.clk = 11100;
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dev_t.t_bacc = 1000;
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dev_t.t_ces = 1000;
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dev_t.t_ceasu = 8 * 1000;
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dev_t.t_avdasu = t_scsnh_advnh - 7000;
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dev_t.t_ce_avd = 1000;
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dev_t.t_avdp_r = t_scsnh_advnh;
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dev_t.cyc_aavdh_oe = 3;
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dev_t.cyc_oe = 5;
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dev_t.t_ce_rdyz = 7000;
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dev_t.t_avdp_w = t_scsnh_advnh;
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dev_t.cyc_aavdh_we = 3;
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dev_t.cyc_wpl = 6;
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dev_t.t_ce_rdyz = 7000;
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/*
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* READ ... based on omap2420 TRM fig 12-19, 12-20
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*/
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/* ADV_RD_OFF = t_scsnh_advnh */
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t.adv_rd_off = next_clk(t.adv_on, t_scsnh_advnh, fclk_ps);
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/* OE_ON = t_scsnh_advnh + t_advn_oen * fclk_ps (then wait for nRDY) */
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tmp = (t.adv_rd_off * 1000) + (3 * fclk_ps);
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t.oe_on = next_clk(t.adv_on, tmp, fclk_ps);
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/* ACCESS = number of clock cycles after t_adv_eon */
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tmp = (t.oe_on * 1000) + (5 * fclk_ps);
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t.access = next_clk(t.oe_on, tmp, fclk_ps);
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/* OE_OFF = after data gets sampled */
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tmp = (t.access * 1000) + (1 * fclk_ps);
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t.oe_off = next_clk(t.access, tmp, fclk_ps);
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t.cs_rd_off = t.oe_off;
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tmp = t.cs_rd_off * 1000 + 7000 /* t_scsn_rdy_z */;
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t.rd_cycle = next_clk(t.cs_rd_off, tmp, fclk_ps);
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/*
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* WRITE ... based on omap2420 TRM fig 12-21
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*/
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/* ADV_WR_OFF = t_scsnh_advnh */
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t.adv_wr_off = t.adv_rd_off;
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/* WE_ON = t_scsnh_advnh + t_advn_wen * fclk_ps (then wait for nRDY) */
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tmp = (t.adv_wr_off * 1000) + (3 * fclk_ps);
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t.we_on = next_clk(t.adv_wr_off, tmp, fclk_ps);
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/* WE_OFF = number of clock cycles after t_adv_wen */
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tmp = (t.we_on * 1000) + (6 * fclk_ps);
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t.we_off = next_clk(t.we_on, tmp, fclk_ps);
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t.cs_wr_off = t.we_off;
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tmp = t.cs_wr_off * 1000 + 7000 /* t_scsn_rdy_z */;
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t.wr_cycle = next_clk(t.cs_wr_off, tmp, fclk_ps);
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t.clk_activation = gpmc_ticks_to_ns(1);
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gpmc_calc_timings(&t, &dev_t);
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return gpmc_cs_set_timings(sync_cs, &t);
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}
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extern unsigned long gpmc_get_fclk_period(void);
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/* tusb driver calls this when it changes the chip's clocking */
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int tusb6010_platform_retime(unsigned is_refclk)
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{
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static const char error[] =
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KERN_ERR "tusb6010 %s retime error %d\n";
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unsigned fclk_ps = gpmc_get_fclk_period();
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unsigned sysclk_ps;
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int status;
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if (!refclk_psec || fclk_ps == 0)
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if (!refclk_psec)
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return -ENODEV;
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sysclk_ps = is_refclk ? refclk_psec : TUSB6010_OSCCLK_60;
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status = tusb_set_async_mode(sysclk_ps, fclk_ps);
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status = tusb_set_async_mode(sysclk_ps);
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if (status < 0) {
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printk(error, "async", status);
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goto done;
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}
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status = tusb_set_sync_mode(sysclk_ps, fclk_ps);
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status = tusb_set_sync_mode(sysclk_ps);
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if (status < 0)
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printk(error, "sync", status);
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done:
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