KVM: x86: Prepare MSR bitmaps for userspace tracked MSRs
Prepare vmx and svm for a subsequent change that ensures the MSR permission bitmap is set to allow an MSR that userspace is tracking to force a vmx_vmexit in the guest. Signed-off-by: Aaron Lewis <aaronlewis@google.com> Reviewed-by: Oliver Upton <oupton@google.com> [agraf: rebase, adapt SVM scheme to nested changes that came in between] Signed-off-by: Alexander Graf <graf@amazon.com> Message-Id: <20200925143422.21718-5-graf@amazon.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
parent
51de8151bd
commit
476c9bd8e9
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@ -564,7 +564,7 @@ static bool valid_msr_intercept(u32 index)
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return false;
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}
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static bool msr_write_intercepted(struct kvm_vcpu *vcpu, unsigned msr)
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static bool msr_write_intercepted(struct kvm_vcpu *vcpu, u32 msr)
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{
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u8 bit_write;
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unsigned long tmp;
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@ -583,7 +583,7 @@ static bool msr_write_intercepted(struct kvm_vcpu *vcpu, unsigned msr)
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return !!test_bit(bit_write, &tmp);
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}
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static void set_msr_interception(u32 *msrpm, unsigned msr,
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static void set_msr_interception(struct kvm_vcpu *vcpu, u32 *msrpm, u32 msr,
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int read, int write)
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{
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u8 bit_read, bit_write;
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@ -609,11 +609,10 @@ static void set_msr_interception(u32 *msrpm, unsigned msr,
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msrpm[offset] = tmp;
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}
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static u32 *svm_vcpu_init_msrpm(void)
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static u32 *svm_vcpu_alloc_msrpm(void)
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{
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int i;
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u32 *msrpm;
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struct page *pages = alloc_pages(GFP_KERNEL_ACCOUNT, MSRPM_ALLOC_ORDER);
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u32 *msrpm;
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if (!pages)
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return NULL;
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@ -621,12 +620,18 @@ static u32 *svm_vcpu_init_msrpm(void)
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msrpm = page_address(pages);
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memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
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return msrpm;
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}
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static void svm_vcpu_init_msrpm(struct kvm_vcpu *vcpu, u32 *msrpm)
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{
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int i;
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for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
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if (!direct_access_msrs[i].always)
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continue;
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set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
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set_msr_interception(vcpu, msrpm, direct_access_msrs[i].index, 1, 1);
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}
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return msrpm;
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}
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static void svm_vcpu_free_msrpm(u32 *msrpm)
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@ -677,26 +682,26 @@ static void init_msrpm_offsets(void)
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}
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}
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static void svm_enable_lbrv(struct vcpu_svm *svm)
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static void svm_enable_lbrv(struct kvm_vcpu *vcpu)
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{
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u32 *msrpm = svm->msrpm;
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struct vcpu_svm *svm = to_svm(vcpu);
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svm->vmcb->control.virt_ext |= LBR_CTL_ENABLE_MASK;
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set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
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set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
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set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
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set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
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set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
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set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
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set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
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set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
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}
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static void svm_disable_lbrv(struct vcpu_svm *svm)
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static void svm_disable_lbrv(struct kvm_vcpu *vcpu)
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{
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u32 *msrpm = svm->msrpm;
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struct vcpu_svm *svm = to_svm(vcpu);
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svm->vmcb->control.virt_ext &= ~LBR_CTL_ENABLE_MASK;
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set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
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set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
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set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
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set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
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set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
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set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
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set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
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set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
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}
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void disable_nmi_singlestep(struct vcpu_svm *svm)
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@ -1230,14 +1235,19 @@ static int svm_create_vcpu(struct kvm_vcpu *vcpu)
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svm->nested.hsave = page_address(hsave_page);
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svm->msrpm = svm_vcpu_init_msrpm();
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svm->msrpm = svm_vcpu_alloc_msrpm();
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if (!svm->msrpm)
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goto error_free_hsave_page;
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svm->nested.msrpm = svm_vcpu_init_msrpm();
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svm_vcpu_init_msrpm(vcpu, svm->msrpm);
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svm->nested.msrpm = svm_vcpu_alloc_msrpm();
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if (!svm->nested.msrpm)
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goto error_free_msrpm;
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/* We only need the L1 pass-through MSR state, so leave vcpu as NULL */
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svm_vcpu_init_msrpm(vcpu, svm->nested.msrpm);
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svm->vmcb = page_address(vmcb_page);
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svm->vmcb_pa = __sme_set(page_to_pfn(vmcb_page) << PAGE_SHIFT);
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svm->asid_generation = 0;
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@ -2574,7 +2584,7 @@ static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
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* We update the L1 MSR bit as well since it will end up
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* touching the MSR anyway now.
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*/
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set_msr_interception(svm->msrpm, MSR_IA32_SPEC_CTRL, 1, 1);
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set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SPEC_CTRL, 1, 1);
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break;
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case MSR_IA32_PRED_CMD:
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if (!msr->host_initiated &&
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@ -2589,7 +2599,7 @@ static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
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break;
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wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
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set_msr_interception(svm->msrpm, MSR_IA32_PRED_CMD, 0, 1);
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set_msr_interception(vcpu, svm->msrpm, MSR_IA32_PRED_CMD, 0, 1);
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break;
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case MSR_AMD64_VIRT_SPEC_CTRL:
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if (!msr->host_initiated &&
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@ -2653,9 +2663,9 @@ static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
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svm->vmcb->save.dbgctl = data;
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vmcb_mark_dirty(svm->vmcb, VMCB_LBR);
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if (data & (1ULL<<0))
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svm_enable_lbrv(svm);
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svm_enable_lbrv(vcpu);
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else
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svm_disable_lbrv(svm);
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svm_disable_lbrv(vcpu);
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break;
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case MSR_VM_HSAVE_PA:
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svm->nested.hsave_msr = data;
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@ -4776,7 +4776,7 @@ static int enter_vmx_operation(struct kvm_vcpu *vcpu)
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if (vmx_pt_mode_is_host_guest()) {
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vmx->pt_desc.guest.ctl = 0;
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pt_update_intercept_for_msr(vmx);
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pt_update_intercept_for_msr(vcpu);
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}
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return 0;
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@ -338,7 +338,7 @@ static const struct kernel_param_ops vmentry_l1d_flush_ops = {
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module_param_cb(vmentry_l1d_flush, &vmentry_l1d_flush_ops, NULL, 0644);
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static u32 vmx_segment_access_rights(struct kvm_segment *var);
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static __always_inline void vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
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static __always_inline void vmx_disable_intercept_for_msr(struct kvm_vcpu *vcpu,
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u32 msr, int type);
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void vmx_vmexit(void);
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@ -1980,7 +1980,7 @@ static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
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* in the merging. We update the vmcs01 here for L1 as well
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* since it will end up touching the MSR anyway now.
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*/
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vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap,
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vmx_disable_intercept_for_msr(vcpu,
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MSR_IA32_SPEC_CTRL,
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MSR_TYPE_RW);
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break;
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@ -2016,8 +2016,7 @@ static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
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* vmcs02.msr_bitmap here since it gets completely overwritten
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* in the merging.
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*/
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vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap, MSR_IA32_PRED_CMD,
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MSR_TYPE_W);
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vmx_disable_intercept_for_msr(vcpu, MSR_IA32_PRED_CMD, MSR_TYPE_W);
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break;
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case MSR_IA32_CR_PAT:
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if (!kvm_pat_valid(data))
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@ -2067,7 +2066,7 @@ static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
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return 1;
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vmcs_write64(GUEST_IA32_RTIT_CTL, data);
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vmx->pt_desc.guest.ctl = data;
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pt_update_intercept_for_msr(vmx);
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pt_update_intercept_for_msr(vcpu);
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break;
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case MSR_IA32_RTIT_STATUS:
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if (!pt_can_write_msr(vmx))
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spin_unlock(&vmx_vpid_lock);
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}
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static __always_inline void vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
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static __always_inline void vmx_disable_intercept_for_msr(struct kvm_vcpu *vcpu,
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u32 msr, int type)
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{
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struct vcpu_vmx *vmx = to_vmx(vcpu);
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unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
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int f = sizeof(unsigned long);
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if (!cpu_has_vmx_msr_bitmap())
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}
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}
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static __always_inline void vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
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static __always_inline void vmx_enable_intercept_for_msr(struct kvm_vcpu *vcpu,
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u32 msr, int type)
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{
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struct vcpu_vmx *vmx = to_vmx(vcpu);
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unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
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int f = sizeof(unsigned long);
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if (!cpu_has_vmx_msr_bitmap())
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}
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}
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static __always_inline void vmx_set_intercept_for_msr(unsigned long *msr_bitmap,
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static __always_inline void vmx_set_intercept_for_msr(struct kvm_vcpu *vcpu,
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u32 msr, int type, bool value)
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{
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if (value)
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vmx_enable_intercept_for_msr(msr_bitmap, msr, type);
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vmx_enable_intercept_for_msr(vcpu, msr, type);
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else
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vmx_disable_intercept_for_msr(msr_bitmap, msr, type);
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vmx_disable_intercept_for_msr(vcpu, msr, type);
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}
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static u8 vmx_msr_bitmap_mode(struct kvm_vcpu *vcpu)
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@ -3684,8 +3687,8 @@ static u8 vmx_msr_bitmap_mode(struct kvm_vcpu *vcpu)
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return mode;
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}
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static void vmx_update_msr_bitmap_x2apic(unsigned long *msr_bitmap,
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u8 mode)
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static void vmx_update_msr_bitmap_x2apic(struct kvm_vcpu *vcpu,
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unsigned long *msr_bitmap, u8 mode)
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{
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int msr;
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@ -3700,11 +3703,11 @@ static void vmx_update_msr_bitmap_x2apic(unsigned long *msr_bitmap,
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* TPR reads and writes can be virtualized even if virtual interrupt
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* delivery is not in use.
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*/
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vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TASKPRI), MSR_TYPE_RW);
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vmx_disable_intercept_for_msr(vcpu, X2APIC_MSR(APIC_TASKPRI), MSR_TYPE_RW);
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if (mode & MSR_BITMAP_MODE_X2APIC_APICV) {
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vmx_enable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TMCCT), MSR_TYPE_R);
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vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_EOI), MSR_TYPE_W);
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vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_SELF_IPI), MSR_TYPE_W);
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vmx_enable_intercept_for_msr(vcpu, X2APIC_MSR(APIC_TMCCT), MSR_TYPE_RW);
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vmx_disable_intercept_for_msr(vcpu, X2APIC_MSR(APIC_EOI), MSR_TYPE_W);
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vmx_disable_intercept_for_msr(vcpu, X2APIC_MSR(APIC_SELF_IPI), MSR_TYPE_W);
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}
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}
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}
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@ -3720,30 +3723,24 @@ void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu)
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return;
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if (changed & (MSR_BITMAP_MODE_X2APIC | MSR_BITMAP_MODE_X2APIC_APICV))
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vmx_update_msr_bitmap_x2apic(msr_bitmap, mode);
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vmx_update_msr_bitmap_x2apic(vcpu, msr_bitmap, mode);
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vmx->msr_bitmap_mode = mode;
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}
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void pt_update_intercept_for_msr(struct vcpu_vmx *vmx)
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void pt_update_intercept_for_msr(struct kvm_vcpu *vcpu)
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{
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unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
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struct vcpu_vmx *vmx = to_vmx(vcpu);
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bool flag = !(vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN);
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u32 i;
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vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_STATUS,
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MSR_TYPE_RW, flag);
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vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_OUTPUT_BASE,
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MSR_TYPE_RW, flag);
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vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_OUTPUT_MASK,
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MSR_TYPE_RW, flag);
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vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_CR3_MATCH,
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MSR_TYPE_RW, flag);
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vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_STATUS, MSR_TYPE_RW, flag);
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vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_OUTPUT_BASE, MSR_TYPE_RW, flag);
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vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_OUTPUT_MASK, MSR_TYPE_RW, flag);
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vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_CR3_MATCH, MSR_TYPE_RW, flag);
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for (i = 0; i < vmx->pt_desc.addr_range; i++) {
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vmx_set_intercept_for_msr(msr_bitmap,
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MSR_IA32_RTIT_ADDR0_A + i * 2, MSR_TYPE_RW, flag);
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vmx_set_intercept_for_msr(msr_bitmap,
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MSR_IA32_RTIT_ADDR0_B + i * 2, MSR_TYPE_RW, flag);
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vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_ADDR0_A + i * 2, MSR_TYPE_RW, flag);
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vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_ADDR0_B + i * 2, MSR_TYPE_RW, flag);
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}
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}
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@ -6753,18 +6750,18 @@ static int vmx_create_vcpu(struct kvm_vcpu *vcpu)
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goto free_pml;
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msr_bitmap = vmx->vmcs01.msr_bitmap;
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vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_TSC, MSR_TYPE_R);
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vmx_disable_intercept_for_msr(msr_bitmap, MSR_FS_BASE, MSR_TYPE_RW);
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vmx_disable_intercept_for_msr(msr_bitmap, MSR_GS_BASE, MSR_TYPE_RW);
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vmx_disable_intercept_for_msr(msr_bitmap, MSR_KERNEL_GS_BASE, MSR_TYPE_RW);
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vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_CS, MSR_TYPE_RW);
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vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_ESP, MSR_TYPE_RW);
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vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_EIP, MSR_TYPE_RW);
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vmx_disable_intercept_for_msr(vcpu, MSR_IA32_TSC, MSR_TYPE_R);
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vmx_disable_intercept_for_msr(vcpu, MSR_FS_BASE, MSR_TYPE_RW);
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vmx_disable_intercept_for_msr(vcpu, MSR_GS_BASE, MSR_TYPE_RW);
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vmx_disable_intercept_for_msr(vcpu, MSR_KERNEL_GS_BASE, MSR_TYPE_RW);
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vmx_disable_intercept_for_msr(vcpu, MSR_IA32_SYSENTER_CS, MSR_TYPE_RW);
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vmx_disable_intercept_for_msr(vcpu, MSR_IA32_SYSENTER_ESP, MSR_TYPE_RW);
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vmx_disable_intercept_for_msr(vcpu, MSR_IA32_SYSENTER_EIP, MSR_TYPE_RW);
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if (kvm_cstate_in_guest(vcpu->kvm)) {
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vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C1_RES, MSR_TYPE_R);
|
||||
vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C3_RESIDENCY, MSR_TYPE_R);
|
||||
vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C6_RESIDENCY, MSR_TYPE_R);
|
||||
vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C7_RESIDENCY, MSR_TYPE_R);
|
||||
vmx_disable_intercept_for_msr(vcpu, MSR_CORE_C1_RES, MSR_TYPE_R);
|
||||
vmx_disable_intercept_for_msr(vcpu, MSR_CORE_C3_RESIDENCY, MSR_TYPE_R);
|
||||
vmx_disable_intercept_for_msr(vcpu, MSR_CORE_C6_RESIDENCY, MSR_TYPE_R);
|
||||
vmx_disable_intercept_for_msr(vcpu, MSR_CORE_C7_RESIDENCY, MSR_TYPE_R);
|
||||
}
|
||||
vmx->msr_bitmap_mode = 0;
|
||||
|
||||
|
|
|
@ -330,7 +330,7 @@ bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu);
|
|||
void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked);
|
||||
void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu);
|
||||
struct vmx_uret_msr *vmx_find_uret_msr(struct vcpu_vmx *vmx, u32 msr);
|
||||
void pt_update_intercept_for_msr(struct vcpu_vmx *vmx);
|
||||
void pt_update_intercept_for_msr(struct kvm_vcpu *vcpu);
|
||||
void vmx_update_host_rsp(struct vcpu_vmx *vmx, unsigned long host_rsp);
|
||||
int vmx_find_loadstore_msr_slot(struct vmx_msrs *m, u32 msr);
|
||||
void vmx_ept_load_pdptrs(struct kvm_vcpu *vcpu);
|
||||
|
|
Loading…
Reference in New Issue