drm/i915: Extract intel_fifo_underrun.c
Prep work for some nice documentation. Requires that we export the display irq enable/disable functions on ilk/ibx. But we already export them for vlv/i915. So not more inconsistency. v2: Rebase on top of skl stage 1. Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
This commit is contained in:
Daniel Vetter
parent
cacc6c837b
commit
47339cd9ff
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@ -45,6 +45,7 @@ i915-y += intel_renderstate_gen6.o \
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# modesetting core code
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i915-y += intel_bios.o \
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intel_display.o \
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intel_fifo_underrun.o \
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intel_frontbuffer.o \
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intel_modes.o \
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intel_overlay.o \
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@ -2312,6 +2312,17 @@ i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
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void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
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void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
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void
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ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask);
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void
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ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask);
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void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
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uint32_t interrupt_mask,
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uint32_t enabled_irq_mask);
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#define ibx_enable_display_interrupt(dev_priv, bits) \
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ibx_display_interrupt_update((dev_priv), (bits), (bits))
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#define ibx_disable_display_interrupt(dev_priv, bits) \
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ibx_display_interrupt_update((dev_priv), (bits), 0)
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/* i915_gem.c */
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int i915_gem_init_ioctl(struct drm_device *dev, void *data,
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@ -139,7 +139,7 @@ static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */
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} while (0)
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/* For display hotplug interrupt */
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static void
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void
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ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask)
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{
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assert_spin_locked(&dev_priv->irq_lock);
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@ -154,7 +154,7 @@ ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask)
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}
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}
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static void
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void
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ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask)
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{
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assert_spin_locked(&dev_priv->irq_lock);
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@ -238,24 +238,6 @@ void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
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snb_update_pm_irq(dev_priv, mask, 0);
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}
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static bool ivb_can_enable_err_int(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_crtc *crtc;
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enum pipe pipe;
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assert_spin_locked(&dev_priv->irq_lock);
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for_each_pipe(dev_priv, pipe) {
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crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
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if (crtc->cpu_fifo_underrun_disabled)
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return false;
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}
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return true;
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}
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/**
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* bdw_update_pm_irq - update GT interrupt 2
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* @dev_priv: driver private
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@ -296,130 +278,15 @@ void gen8_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
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bdw_update_pm_irq(dev_priv, mask, 0);
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}
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static bool cpt_can_enable_serr_int(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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enum pipe pipe;
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struct intel_crtc *crtc;
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assert_spin_locked(&dev_priv->irq_lock);
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for_each_pipe(dev_priv, pipe) {
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crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
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if (crtc->pch_fifo_underrun_disabled)
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return false;
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}
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return true;
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}
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void i9xx_check_fifo_underruns(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_crtc *crtc;
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spin_lock_irq(&dev_priv->irq_lock);
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for_each_intel_crtc(dev, crtc) {
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u32 reg = PIPESTAT(crtc->pipe);
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u32 pipestat;
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if (crtc->cpu_fifo_underrun_disabled)
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continue;
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pipestat = I915_READ(reg) & 0xffff0000;
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if ((pipestat & PIPE_FIFO_UNDERRUN_STATUS) == 0)
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continue;
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I915_WRITE(reg, pipestat | PIPE_FIFO_UNDERRUN_STATUS);
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POSTING_READ(reg);
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DRM_ERROR("pipe %c underrun\n", pipe_name(crtc->pipe));
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}
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spin_unlock_irq(&dev_priv->irq_lock);
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}
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static void i9xx_set_fifo_underrun_reporting(struct drm_device *dev,
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enum pipe pipe,
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bool enable, bool old)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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u32 reg = PIPESTAT(pipe);
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u32 pipestat = I915_READ(reg) & 0xffff0000;
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assert_spin_locked(&dev_priv->irq_lock);
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if (enable) {
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I915_WRITE(reg, pipestat | PIPE_FIFO_UNDERRUN_STATUS);
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POSTING_READ(reg);
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} else {
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if (old && pipestat & PIPE_FIFO_UNDERRUN_STATUS)
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DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
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}
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}
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static void ironlake_set_fifo_underrun_reporting(struct drm_device *dev,
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enum pipe pipe, bool enable)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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uint32_t bit = (pipe == PIPE_A) ? DE_PIPEA_FIFO_UNDERRUN :
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DE_PIPEB_FIFO_UNDERRUN;
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if (enable)
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ironlake_enable_display_irq(dev_priv, bit);
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else
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ironlake_disable_display_irq(dev_priv, bit);
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}
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static void ivybridge_set_fifo_underrun_reporting(struct drm_device *dev,
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enum pipe pipe,
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bool enable, bool old)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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if (enable) {
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I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe));
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if (!ivb_can_enable_err_int(dev))
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return;
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ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB);
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} else {
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ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB);
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if (old &&
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I915_READ(GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe)) {
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DRM_ERROR("uncleared fifo underrun on pipe %c\n",
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pipe_name(pipe));
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}
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}
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}
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static void broadwell_set_fifo_underrun_reporting(struct drm_device *dev,
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enum pipe pipe, bool enable)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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assert_spin_locked(&dev_priv->irq_lock);
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if (enable)
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dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_FIFO_UNDERRUN;
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else
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dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_FIFO_UNDERRUN;
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I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
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POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
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}
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/**
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* ibx_display_interrupt_update - update SDEIMR
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* @dev_priv: driver private
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* @interrupt_mask: mask of interrupt bits to update
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* @enabled_irq_mask: mask of interrupt bits to enable
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*/
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static void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
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uint32_t interrupt_mask,
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uint32_t enabled_irq_mask)
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void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
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uint32_t interrupt_mask,
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uint32_t enabled_irq_mask)
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{
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uint32_t sdeimr = I915_READ(SDEIMR);
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sdeimr &= ~interrupt_mask;
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@ -433,160 +300,6 @@ static void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
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I915_WRITE(SDEIMR, sdeimr);
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POSTING_READ(SDEIMR);
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}
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#define ibx_enable_display_interrupt(dev_priv, bits) \
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ibx_display_interrupt_update((dev_priv), (bits), (bits))
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#define ibx_disable_display_interrupt(dev_priv, bits) \
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ibx_display_interrupt_update((dev_priv), (bits), 0)
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static void ibx_set_fifo_underrun_reporting(struct drm_device *dev,
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enum transcoder pch_transcoder,
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bool enable)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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uint32_t bit = (pch_transcoder == TRANSCODER_A) ?
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SDE_TRANSA_FIFO_UNDER : SDE_TRANSB_FIFO_UNDER;
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if (enable)
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ibx_enable_display_interrupt(dev_priv, bit);
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else
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ibx_disable_display_interrupt(dev_priv, bit);
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}
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static void cpt_set_fifo_underrun_reporting(struct drm_device *dev,
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enum transcoder pch_transcoder,
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bool enable, bool old)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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if (enable) {
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I915_WRITE(SERR_INT,
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SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder));
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if (!cpt_can_enable_serr_int(dev))
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return;
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ibx_enable_display_interrupt(dev_priv, SDE_ERROR_CPT);
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} else {
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ibx_disable_display_interrupt(dev_priv, SDE_ERROR_CPT);
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if (old && I915_READ(SERR_INT) &
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SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)) {
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DRM_ERROR("uncleared pch fifo underrun on pch transcoder %c\n",
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transcoder_name(pch_transcoder));
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}
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}
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}
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/**
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* intel_set_cpu_fifo_underrun_reporting - enable/disable FIFO underrun messages
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* @dev: drm device
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* @pipe: pipe
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* @enable: true if we want to report FIFO underrun errors, false otherwise
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*
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* This function makes us disable or enable CPU fifo underruns for a specific
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* pipe. Notice that on some Gens (e.g. IVB, HSW), disabling FIFO underrun
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* reporting for one pipe may also disable all the other CPU error interruts for
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* the other pipes, due to the fact that there's just one interrupt mask/enable
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* bit for all the pipes.
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*
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* Returns the previous state of underrun reporting.
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*/
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static bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
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enum pipe pipe, bool enable)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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bool old;
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assert_spin_locked(&dev_priv->irq_lock);
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old = !intel_crtc->cpu_fifo_underrun_disabled;
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intel_crtc->cpu_fifo_underrun_disabled = !enable;
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if (HAS_GMCH_DISPLAY(dev))
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i9xx_set_fifo_underrun_reporting(dev, pipe, enable, old);
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else if (IS_GEN5(dev) || IS_GEN6(dev))
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ironlake_set_fifo_underrun_reporting(dev, pipe, enable);
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else if (IS_GEN7(dev))
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ivybridge_set_fifo_underrun_reporting(dev, pipe, enable, old);
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else if (IS_GEN8(dev) || IS_GEN9(dev))
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broadwell_set_fifo_underrun_reporting(dev, pipe, enable);
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return old;
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}
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bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
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enum pipe pipe, bool enable)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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unsigned long flags;
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bool ret;
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spin_lock_irqsave(&dev_priv->irq_lock, flags);
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ret = __intel_set_cpu_fifo_underrun_reporting(dev, pipe, enable);
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spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
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return ret;
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}
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static bool __cpu_fifo_underrun_reporting_enabled(struct drm_device *dev,
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enum pipe pipe)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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return !intel_crtc->cpu_fifo_underrun_disabled;
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}
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/**
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* intel_set_pch_fifo_underrun_reporting - enable/disable FIFO underrun messages
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* @dev: drm device
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* @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
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* @enable: true if we want to report FIFO underrun errors, false otherwise
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*
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* This function makes us disable or enable PCH fifo underruns for a specific
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* PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO
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* underrun reporting for one transcoder may also disable all the other PCH
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* error interruts for the other transcoders, due to the fact that there's just
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* one interrupt mask/enable bit for all the transcoders.
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*
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* Returns the previous state of underrun reporting.
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*/
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bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
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enum transcoder pch_transcoder,
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bool enable)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pch_transcoder];
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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unsigned long flags;
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bool old;
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/*
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* NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT
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* has only one pch transcoder A that all pipes can use. To avoid racy
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* pch transcoder -> pipe lookups from interrupt code simply store the
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* underrun statistics in crtc A. Since we never expose this anywhere
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* nor use it outside of the fifo underrun code here using the "wrong"
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* crtc on LPT won't cause issues.
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*/
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spin_lock_irqsave(&dev_priv->irq_lock, flags);
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old = !intel_crtc->pch_fifo_underrun_disabled;
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intel_crtc->pch_fifo_underrun_disabled = !enable;
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if (HAS_PCH_IBX(dev))
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ibx_set_fifo_underrun_reporting(dev, pch_transcoder, enable);
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else
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cpt_set_fifo_underrun_reporting(dev, pch_transcoder, enable, old);
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spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
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return old;
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}
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static void
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__i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
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@ -755,12 +755,17 @@ static inline unsigned int intel_num_planes(struct intel_crtc *crtc)
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return INTEL_INFO(crtc->base.dev)->num_sprites[crtc->pipe] + 1;
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}
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/* i915_irq.c */
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/* intel_fifo_underrun.c */
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bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
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enum pipe pipe, bool enable);
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bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
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enum transcoder pch_transcoder,
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bool enable);
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void i9xx_check_fifo_underruns(struct drm_device *dev);
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bool __cpu_fifo_underrun_reporting_enabled(struct drm_device *dev,
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enum pipe pipe);
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/* i915_irq.c */
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void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
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void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
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void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
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@ -779,7 +784,6 @@ static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
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}
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int intel_get_crtc_scanline(struct intel_crtc *crtc);
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void i9xx_check_fifo_underruns(struct drm_device *dev);
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void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv);
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/* intel_crt.c */
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@ -0,0 +1,311 @@
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/*
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* Copyright © 2014 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
|
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
|
||||
* IN THE SOFTWARE.
|
||||
*
|
||||
* Authors:
|
||||
* Daniel Vetter <daniel.vetter@ffwll.ch>
|
||||
*
|
||||
*/
|
||||
|
||||
#include "i915_drv.h"
|
||||
#include "intel_drv.h"
|
||||
|
||||
static bool ivb_can_enable_err_int(struct drm_device *dev)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = dev->dev_private;
|
||||
struct intel_crtc *crtc;
|
||||
enum pipe pipe;
|
||||
|
||||
assert_spin_locked(&dev_priv->irq_lock);
|
||||
|
||||
for_each_pipe(dev_priv, pipe) {
|
||||
crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
|
||||
|
||||
if (crtc->cpu_fifo_underrun_disabled)
|
||||
return false;
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
static bool cpt_can_enable_serr_int(struct drm_device *dev)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = dev->dev_private;
|
||||
enum pipe pipe;
|
||||
struct intel_crtc *crtc;
|
||||
|
||||
assert_spin_locked(&dev_priv->irq_lock);
|
||||
|
||||
for_each_pipe(dev_priv, pipe) {
|
||||
crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
|
||||
|
||||
if (crtc->pch_fifo_underrun_disabled)
|
||||
return false;
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
void i9xx_check_fifo_underruns(struct drm_device *dev)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = dev->dev_private;
|
||||
struct intel_crtc *crtc;
|
||||
|
||||
spin_lock_irq(&dev_priv->irq_lock);
|
||||
|
||||
for_each_intel_crtc(dev, crtc) {
|
||||
u32 reg = PIPESTAT(crtc->pipe);
|
||||
u32 pipestat;
|
||||
|
||||
if (crtc->cpu_fifo_underrun_disabled)
|
||||
continue;
|
||||
|
||||
pipestat = I915_READ(reg) & 0xffff0000;
|
||||
if ((pipestat & PIPE_FIFO_UNDERRUN_STATUS) == 0)
|
||||
continue;
|
||||
|
||||
I915_WRITE(reg, pipestat | PIPE_FIFO_UNDERRUN_STATUS);
|
||||
POSTING_READ(reg);
|
||||
|
||||
DRM_ERROR("pipe %c underrun\n", pipe_name(crtc->pipe));
|
||||
}
|
||||
|
||||
spin_unlock_irq(&dev_priv->irq_lock);
|
||||
}
|
||||
|
||||
static void i9xx_set_fifo_underrun_reporting(struct drm_device *dev,
|
||||
enum pipe pipe,
|
||||
bool enable, bool old)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = dev->dev_private;
|
||||
u32 reg = PIPESTAT(pipe);
|
||||
u32 pipestat = I915_READ(reg) & 0xffff0000;
|
||||
|
||||
assert_spin_locked(&dev_priv->irq_lock);
|
||||
|
||||
if (enable) {
|
||||
I915_WRITE(reg, pipestat | PIPE_FIFO_UNDERRUN_STATUS);
|
||||
POSTING_READ(reg);
|
||||
} else {
|
||||
if (old && pipestat & PIPE_FIFO_UNDERRUN_STATUS)
|
||||
DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
|
||||
}
|
||||
}
|
||||
|
||||
static void ironlake_set_fifo_underrun_reporting(struct drm_device *dev,
|
||||
enum pipe pipe, bool enable)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = dev->dev_private;
|
||||
uint32_t bit = (pipe == PIPE_A) ? DE_PIPEA_FIFO_UNDERRUN :
|
||||
DE_PIPEB_FIFO_UNDERRUN;
|
||||
|
||||
if (enable)
|
||||
ironlake_enable_display_irq(dev_priv, bit);
|
||||
else
|
||||
ironlake_disable_display_irq(dev_priv, bit);
|
||||
}
|
||||
|
||||
static void ivybridge_set_fifo_underrun_reporting(struct drm_device *dev,
|
||||
enum pipe pipe,
|
||||
bool enable, bool old)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = dev->dev_private;
|
||||
if (enable) {
|
||||
I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe));
|
||||
|
||||
if (!ivb_can_enable_err_int(dev))
|
||||
return;
|
||||
|
||||
ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB);
|
||||
} else {
|
||||
ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB);
|
||||
|
||||
if (old &&
|
||||
I915_READ(GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe)) {
|
||||
DRM_ERROR("uncleared fifo underrun on pipe %c\n",
|
||||
pipe_name(pipe));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void broadwell_set_fifo_underrun_reporting(struct drm_device *dev,
|
||||
enum pipe pipe, bool enable)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = dev->dev_private;
|
||||
|
||||
assert_spin_locked(&dev_priv->irq_lock);
|
||||
|
||||
if (enable)
|
||||
dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_FIFO_UNDERRUN;
|
||||
else
|
||||
dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_FIFO_UNDERRUN;
|
||||
I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
|
||||
POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
|
||||
}
|
||||
|
||||
static void ibx_set_fifo_underrun_reporting(struct drm_device *dev,
|
||||
enum transcoder pch_transcoder,
|
||||
bool enable)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = dev->dev_private;
|
||||
uint32_t bit = (pch_transcoder == TRANSCODER_A) ?
|
||||
SDE_TRANSA_FIFO_UNDER : SDE_TRANSB_FIFO_UNDER;
|
||||
|
||||
if (enable)
|
||||
ibx_enable_display_interrupt(dev_priv, bit);
|
||||
else
|
||||
ibx_disable_display_interrupt(dev_priv, bit);
|
||||
}
|
||||
|
||||
static void cpt_set_fifo_underrun_reporting(struct drm_device *dev,
|
||||
enum transcoder pch_transcoder,
|
||||
bool enable, bool old)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = dev->dev_private;
|
||||
|
||||
if (enable) {
|
||||
I915_WRITE(SERR_INT,
|
||||
SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder));
|
||||
|
||||
if (!cpt_can_enable_serr_int(dev))
|
||||
return;
|
||||
|
||||
ibx_enable_display_interrupt(dev_priv, SDE_ERROR_CPT);
|
||||
} else {
|
||||
ibx_disable_display_interrupt(dev_priv, SDE_ERROR_CPT);
|
||||
|
||||
if (old && I915_READ(SERR_INT) &
|
||||
SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)) {
|
||||
DRM_ERROR("uncleared pch fifo underrun on pch transcoder %c\n",
|
||||
transcoder_name(pch_transcoder));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* intel_set_cpu_fifo_underrun_reporting - enable/disable FIFO underrun messages
|
||||
* @dev: drm device
|
||||
* @pipe: pipe
|
||||
* @enable: true if we want to report FIFO underrun errors, false otherwise
|
||||
*
|
||||
* This function makes us disable or enable CPU fifo underruns for a specific
|
||||
* pipe. Notice that on some Gens (e.g. IVB, HSW), disabling FIFO underrun
|
||||
* reporting for one pipe may also disable all the other CPU error interruts for
|
||||
* the other pipes, due to the fact that there's just one interrupt mask/enable
|
||||
* bit for all the pipes.
|
||||
*
|
||||
* Returns the previous state of underrun reporting.
|
||||
*/
|
||||
static bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
|
||||
enum pipe pipe, bool enable)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = dev->dev_private;
|
||||
struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
|
||||
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
|
||||
bool old;
|
||||
|
||||
assert_spin_locked(&dev_priv->irq_lock);
|
||||
|
||||
old = !intel_crtc->cpu_fifo_underrun_disabled;
|
||||
intel_crtc->cpu_fifo_underrun_disabled = !enable;
|
||||
|
||||
if (HAS_GMCH_DISPLAY(dev))
|
||||
i9xx_set_fifo_underrun_reporting(dev, pipe, enable, old);
|
||||
else if (IS_GEN5(dev) || IS_GEN6(dev))
|
||||
ironlake_set_fifo_underrun_reporting(dev, pipe, enable);
|
||||
else if (IS_GEN7(dev))
|
||||
ivybridge_set_fifo_underrun_reporting(dev, pipe, enable, old);
|
||||
else if (IS_GEN8(dev) || IS_GEN9(dev))
|
||||
broadwell_set_fifo_underrun_reporting(dev, pipe, enable);
|
||||
|
||||
return old;
|
||||
}
|
||||
|
||||
bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
|
||||
enum pipe pipe, bool enable)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = dev->dev_private;
|
||||
unsigned long flags;
|
||||
bool ret;
|
||||
|
||||
spin_lock_irqsave(&dev_priv->irq_lock, flags);
|
||||
ret = __intel_set_cpu_fifo_underrun_reporting(dev, pipe, enable);
|
||||
spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
bool __cpu_fifo_underrun_reporting_enabled(struct drm_device *dev,
|
||||
enum pipe pipe)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = dev->dev_private;
|
||||
struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
|
||||
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
|
||||
|
||||
return !intel_crtc->cpu_fifo_underrun_disabled;
|
||||
}
|
||||
|
||||
/**
|
||||
* intel_set_pch_fifo_underrun_reporting - enable/disable FIFO underrun messages
|
||||
* @dev: drm device
|
||||
* @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
|
||||
* @enable: true if we want to report FIFO underrun errors, false otherwise
|
||||
*
|
||||
* This function makes us disable or enable PCH fifo underruns for a specific
|
||||
* PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO
|
||||
* underrun reporting for one transcoder may also disable all the other PCH
|
||||
* error interruts for the other transcoders, due to the fact that there's just
|
||||
* one interrupt mask/enable bit for all the transcoders.
|
||||
*
|
||||
* Returns the previous state of underrun reporting.
|
||||
*/
|
||||
bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
|
||||
enum transcoder pch_transcoder,
|
||||
bool enable)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = dev->dev_private;
|
||||
struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pch_transcoder];
|
||||
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
|
||||
unsigned long flags;
|
||||
bool old;
|
||||
|
||||
/*
|
||||
* NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT
|
||||
* has only one pch transcoder A that all pipes can use. To avoid racy
|
||||
* pch transcoder -> pipe lookups from interrupt code simply store the
|
||||
* underrun statistics in crtc A. Since we never expose this anywhere
|
||||
* nor use it outside of the fifo underrun code here using the "wrong"
|
||||
* crtc on LPT won't cause issues.
|
||||
*/
|
||||
|
||||
spin_lock_irqsave(&dev_priv->irq_lock, flags);
|
||||
|
||||
old = !intel_crtc->pch_fifo_underrun_disabled;
|
||||
intel_crtc->pch_fifo_underrun_disabled = !enable;
|
||||
|
||||
if (HAS_PCH_IBX(dev))
|
||||
ibx_set_fifo_underrun_reporting(dev, pch_transcoder, enable);
|
||||
else
|
||||
cpt_set_fifo_underrun_reporting(dev, pch_transcoder, enable, old);
|
||||
|
||||
spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
|
||||
return old;
|
||||
}
|
||||
Loading…
Reference in New Issue