media: dt-bindings: media: camss: Add qcom,sm8250-camss binding
Add bindings for qcom,sm8250-camss in order to support the camera subsystem for SM8250. Cc: devicetree@vger.kernel.org Signed-off-by: Jonathan Marek <jonathan@marek.ca> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl> Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
This commit is contained in:
Jonathan Marek
Mauro Carvalho Chehab
parent
7eba1e4327
commit
46f8ac8497
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/media/qcom,sm8250-camss.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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title: Qualcomm CAMSS ISP
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maintainers:
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- Robert Foss <robert.foss@linaro.org>
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description: |
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The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms.
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properties:
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compatible:
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const: qcom,sm8250-camss
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clocks:
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minItems: 37
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maxItems: 37
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clock-names:
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items:
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- const: cam_ahb_clk
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- const: cam_hf_axi
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- const: cam_sf_axi
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- const: camnoc_axi
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- const: camnoc_axi_src
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- const: core_ahb
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- const: cpas_ahb
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- const: csiphy0
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- const: csiphy0_timer
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- const: csiphy1
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- const: csiphy1_timer
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- const: csiphy2
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- const: csiphy2_timer
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- const: csiphy3
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- const: csiphy3_timer
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- const: csiphy4
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- const: csiphy4_timer
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- const: csiphy5
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- const: csiphy5_timer
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- const: slow_ahb_src
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- const: vfe0_ahb
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- const: vfe0_axi
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- const: vfe0
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- const: vfe0_cphy_rx
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- const: vfe0_csid
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- const: vfe0_areg
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- const: vfe1_ahb
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- const: vfe1_axi
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- const: vfe1
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- const: vfe1_cphy_rx
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- const: vfe1_csid
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- const: vfe1_areg
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- const: vfe_lite_ahb
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- const: vfe_lite_axi
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- const: vfe_lite
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- const: vfe_lite_cphy_rx
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- const: vfe_lite_csid
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interrupts:
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minItems: 14
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maxItems: 14
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interrupt-names:
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items:
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- const: csiphy0
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- const: csiphy1
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- const: csiphy2
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- const: csiphy3
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- const: csiphy4
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- const: csiphy5
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- const: csid0
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- const: csid1
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- const: csid2
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- const: csid3
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- const: vfe0
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- const: vfe1
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- const: vfe_lite0
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- const: vfe_lite1
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iommus:
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minItems: 8
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maxItems: 8
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interconnects:
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minItems: 4
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maxItems: 4
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interconnect-names:
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items:
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- const: cam_ahb
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- const: cam_hf_0_mnoc
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- const: cam_sf_0_mnoc
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- const: cam_sf_icp_mnoc
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power-domains:
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items:
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- description: IFE0 GDSC - Image Front End, Global Distributed Switch Controller.
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- description: IFE1 GDSC - Image Front End, Global Distributed Switch Controller.
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- description: Titan GDSC - Titan ISP Block, Global Distributed Switch Controller.
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ports:
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$ref: /schemas/graph.yaml#/properties/ports
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description:
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CSI input ports.
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properties:
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port@0:
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$ref: /schemas/graph.yaml#/$defs/port-base
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unevaluatedProperties: false
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description:
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Input port for receiving CSI data.
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properties:
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endpoint:
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$ref: video-interfaces.yaml#
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unevaluatedProperties: false
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properties:
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clock-lanes:
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maxItems: 1
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data-lanes:
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minItems: 1
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maxItems: 4
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required:
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- clock-lanes
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- data-lanes
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port@1:
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$ref: /schemas/graph.yaml#/$defs/port-base
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unevaluatedProperties: false
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description:
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Input port for receiving CSI data.
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properties:
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endpoint:
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$ref: video-interfaces.yaml#
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unevaluatedProperties: false
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properties:
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clock-lanes:
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maxItems: 1
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data-lanes:
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minItems: 1
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maxItems: 4
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required:
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- clock-lanes
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- data-lanes
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port@2:
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$ref: /schemas/graph.yaml#/$defs/port-base
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unevaluatedProperties: false
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description:
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Input port for receiving CSI data.
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properties:
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endpoint:
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$ref: video-interfaces.yaml#
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unevaluatedProperties: false
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properties:
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clock-lanes:
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maxItems: 1
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data-lanes:
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minItems: 1
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maxItems: 4
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required:
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- clock-lanes
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- data-lanes
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port@3:
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$ref: /schemas/graph.yaml#/$defs/port-base
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unevaluatedProperties: false
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description:
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Input port for receiving CSI data.
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properties:
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endpoint:
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$ref: video-interfaces.yaml#
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unevaluatedProperties: false
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properties:
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clock-lanes:
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maxItems: 1
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data-lanes:
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minItems: 1
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maxItems: 4
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required:
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- clock-lanes
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- data-lanes
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port@4:
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$ref: /schemas/graph.yaml#/$defs/port-base
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unevaluatedProperties: false
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description:
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Input port for receiving CSI data.
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properties:
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endpoint:
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$ref: video-interfaces.yaml#
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unevaluatedProperties: false
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properties:
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clock-lanes:
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maxItems: 1
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data-lanes:
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minItems: 1
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maxItems: 4
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required:
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- clock-lanes
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- data-lanes
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port@5:
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$ref: /schemas/graph.yaml#/$defs/port-base
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unevaluatedProperties: false
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description:
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Input port for receiving CSI data.
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properties:
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endpoint:
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$ref: video-interfaces.yaml#
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unevaluatedProperties: false
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properties:
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clock-lanes:
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maxItems: 1
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data-lanes:
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minItems: 1
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maxItems: 4
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required:
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- clock-lanes
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- data-lanes
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reg:
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minItems: 10
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maxItems: 10
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reg-names:
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items:
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- const: csiphy0
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- const: csiphy1
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- const: csiphy2
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- const: csiphy3
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- const: csiphy4
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- const: csiphy5
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- const: vfe0
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- const: vfe1
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- const: vfe_lite0
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- const: vfe_lite1
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required:
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- clock-names
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- clocks
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- compatible
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- interconnects
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- interconnect-names
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- interrupts
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- interrupt-names
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- iommus
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- power-domains
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- reg
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- reg-names
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/qcom,camcc-sm8250.h>
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#include <dt-bindings/interconnect/qcom,sm8250.h>
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#include <dt-bindings/clock/qcom,gcc-sm8250.h>
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#include <dt-bindings/power/qcom-rpmpd.h>
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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camss: camss@ac6a000 {
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compatible = "qcom,sm8250-camss";
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reg = <0 0xac6a000 0 0x2000>,
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<0 0xac6c000 0 0x2000>,
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<0 0xac6e000 0 0x1000>,
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<0 0xac70000 0 0x1000>,
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<0 0xac72000 0 0x1000>,
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<0 0xac74000 0 0x1000>,
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<0 0xacb4000 0 0xd000>,
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<0 0xacc3000 0 0xd000>,
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<0 0xacd9000 0 0x2200>,
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<0 0xacdb200 0 0x2200>;
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reg-names = "csiphy0",
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"csiphy1",
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"csiphy2",
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"csiphy3",
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"csiphy4",
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"csiphy5",
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"vfe0",
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"vfe1",
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"vfe_lite0",
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"vfe_lite1";
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interrupts = <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "csiphy0",
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"csiphy1",
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"csiphy2",
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"csiphy3",
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"csiphy4",
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"csiphy5",
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"csid0",
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"csid1",
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"csid2",
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"csid3",
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"vfe0",
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"vfe1",
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"vfe_lite0",
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"vfe_lite1";
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power-domains = <&camcc IFE_0_GDSC>,
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<&camcc IFE_1_GDSC>,
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<&camcc TITAN_TOP_GDSC>;
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clocks = <&gcc GCC_CAMERA_AHB_CLK>,
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<&gcc GCC_CAMERA_HF_AXI_CLK>,
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<&gcc GCC_CAMERA_SF_AXI_CLK>,
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<&camcc CAM_CC_CAMNOC_AXI_CLK>,
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<&camcc CAM_CC_CAMNOC_AXI_CLK_SRC>,
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<&camcc CAM_CC_CORE_AHB_CLK>,
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<&camcc CAM_CC_CPAS_AHB_CLK>,
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<&camcc CAM_CC_CSIPHY0_CLK>,
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<&camcc CAM_CC_CSI0PHYTIMER_CLK>,
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<&camcc CAM_CC_CSIPHY1_CLK>,
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<&camcc CAM_CC_CSI1PHYTIMER_CLK>,
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<&camcc CAM_CC_CSIPHY2_CLK>,
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<&camcc CAM_CC_CSI2PHYTIMER_CLK>,
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<&camcc CAM_CC_CSIPHY3_CLK>,
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<&camcc CAM_CC_CSI3PHYTIMER_CLK>,
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<&camcc CAM_CC_CSIPHY4_CLK>,
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<&camcc CAM_CC_CSI4PHYTIMER_CLK>,
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<&camcc CAM_CC_CSIPHY5_CLK>,
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<&camcc CAM_CC_CSI5PHYTIMER_CLK>,
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<&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
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<&camcc CAM_CC_IFE_0_AHB_CLK>,
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<&camcc CAM_CC_IFE_0_AXI_CLK>,
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<&camcc CAM_CC_IFE_0_CLK>,
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<&camcc CAM_CC_IFE_0_CPHY_RX_CLK>,
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<&camcc CAM_CC_IFE_0_CSID_CLK>,
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<&camcc CAM_CC_IFE_0_AREG_CLK>,
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<&camcc CAM_CC_IFE_1_AHB_CLK>,
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<&camcc CAM_CC_IFE_1_AXI_CLK>,
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<&camcc CAM_CC_IFE_1_CLK>,
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<&camcc CAM_CC_IFE_1_CPHY_RX_CLK>,
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<&camcc CAM_CC_IFE_1_CSID_CLK>,
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<&camcc CAM_CC_IFE_1_AREG_CLK>,
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<&camcc CAM_CC_IFE_LITE_AHB_CLK>,
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<&camcc CAM_CC_IFE_LITE_AXI_CLK>,
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<&camcc CAM_CC_IFE_LITE_CLK>,
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<&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
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<&camcc CAM_CC_IFE_LITE_CSID_CLK>;
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clock-names = "cam_ahb_clk",
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"cam_hf_axi",
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"cam_sf_axi",
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"camnoc_axi",
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"camnoc_axi_src",
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"core_ahb",
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"cpas_ahb",
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"csiphy0",
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"csiphy0_timer",
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"csiphy1",
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"csiphy1_timer",
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"csiphy2",
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"csiphy2_timer",
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"csiphy3",
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"csiphy3_timer",
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"csiphy4",
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"csiphy4_timer",
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"csiphy5",
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"csiphy5_timer",
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"slow_ahb_src",
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"vfe0_ahb",
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"vfe0_axi",
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"vfe0",
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"vfe0_cphy_rx",
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"vfe0_csid",
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"vfe0_areg",
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"vfe1_ahb",
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"vfe1_axi",
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"vfe1",
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"vfe1_cphy_rx",
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"vfe1_csid",
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"vfe1_areg",
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"vfe_lite_ahb",
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"vfe_lite_axi",
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"vfe_lite",
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"vfe_lite_cphy_rx",
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"vfe_lite_csid";
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iommus = <&apps_smmu 0x800 0x400>,
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<&apps_smmu 0x801 0x400>,
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<&apps_smmu 0x840 0x400>,
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<&apps_smmu 0x841 0x400>,
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<&apps_smmu 0xC00 0x400>,
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<&apps_smmu 0xC01 0x400>,
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<&apps_smmu 0xC40 0x400>,
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<&apps_smmu 0xC41 0x400>;
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interconnects = <&gem_noc MASTER_AMPSS_M0 &config_noc SLAVE_CAMERA_CFG>,
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<&mmss_noc MASTER_CAMNOC_HF &mc_virt SLAVE_EBI_CH0>,
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<&mmss_noc MASTER_CAMNOC_SF &mc_virt SLAVE_EBI_CH0>,
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<&mmss_noc MASTER_CAMNOC_ICP &mc_virt SLAVE_EBI_CH0>;
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interconnect-names = "cam_ahb",
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"cam_hf_0_mnoc",
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"cam_sf_0_mnoc",
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"cam_sf_icp_mnoc";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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};
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