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arm64/sysreg: Convert TRBSR_EL1 register to automatic generation 

This converts TRBSR_EL1 register to automatic generation without
causing any functional change.

Cc: Will Deacon <will@kernel.org>
Cc: Marc Zyngier <maz@kernel.org>
Cc: Mark Brown <broonie@kernel.org>
Cc: Rob Herring <robh@kernel.org>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: James Morse <james.morse@arm.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Reviewed-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Link: https://lore.kernel.org/r/20230614065949.146187-12-anshuman.khandual@arm.com
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
This commit is contained in:
Anshuman Khandual 2023-06-14 12:29:46 +05:30 committed by Catalin Marinas
parent cbaf0cf005
commit 46f3a5b01f
2 changed files with 16 additions and 12 deletions
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12
arch/arm64/include/asm/sysreg.h
View File

@ -227,24 +227,12 @@
/*** End of Statistical Profiling Extension ***/
#define SYS_TRBSR_EL1 sys_reg(3, 0, 9, 11, 3)
#define SYS_TRBMAR_EL1 sys_reg(3, 0, 9, 11, 4)
#define SYS_TRBTRG_EL1 sys_reg(3, 0, 9, 11, 6)
#define SYS_TRBIDR_EL1 sys_reg(3, 0, 9, 11, 7)
#define TRBSR_EL1_EC_MASK GENMASK(31, 26)
#define TRBSR_EL1_EC_SHIFT 26
#define TRBSR_EL1_IRQ BIT(22)
#define TRBSR_EL1_TRG BIT(21)
#define TRBSR_EL1_WRAP BIT(20)
#define TRBSR_EL1_EA BIT(18)
#define TRBSR_EL1_S BIT(17)
#define TRBSR_EL1_MSS_MASK GENMASK(15, 0)
#define TRBSR_EL1_MSS_SHIFT 0
#define TRBSR_EL1_BSC_MASK GENMASK(5, 0)
#define TRBSR_EL1_BSC_SHIFT 0
#define TRBSR_EL1_FSC_MASK GENMASK(5, 0)
#define TRBSR_EL1_FSC_SHIFT 0
#define TRBMAR_EL1_SH_MASK GENMASK(9, 8)
#define TRBMAR_EL1_SH_SHIFT 8
#define TRBMAR_EL1_Attr_MASK GENMASK(7, 0)

16
arch/arm64/tools/sysreg
View File

@ -2282,3 +2282,19 @@ Sysreg TRBBASER_EL1 3 0 9 11 2
Field 63:12 BASE
Res0 11:0
EndSysreg
Sysreg TRBSR_EL1 3 0 9 11 3
Res0 63:56
Field 55:32 MSS2
Field 31:26 EC
Res0 25:24
Field 23 DAT
Field 22 IRQ
Field 21 TRG
Field 20 WRAP
Res0 19
Field 18 EA
Field 17 S
Res0 16
Field 15:0 MSS
EndSysreg