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MIPS: SGI-IP28: disable use of ll/sc in kernel 

SGI-IP28 systems only use broken R10k rev 2.5 CPUs, which could lock
up, if ll/sc sequences are issued in certain order. Since those systems
are all non-SMP, we can disable ll/sc usage in kernel.

Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
This commit is contained in:
Thomas Bogendoerfer 2020-10-07 12:17:04 +02:00
parent 43fab0856e
commit 46dd40aa37
1 changed files with 1 additions and 1 deletions
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2
arch/mips/include/asm/mach-ip28/cpu-feature-overrides.h
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@ -25,7 +25,7 @@
#define cpu_has_mcheck 0 #define cpu_has_mcheck 0
#define cpu_has_ejtag 0 #define cpu_has_ejtag 0
#define cpu_has_llsc 1 #define cpu_has_llsc 0
#define cpu_has_vtag_icache 0 #define cpu_has_vtag_icache 0
#define cpu_has_dc_aliases 0 /* see probe_pcache() */ #define cpu_has_dc_aliases 0 /* see probe_pcache() */
#define cpu_has_ic_fills_f_dc 0 #define cpu_has_ic_fills_f_dc 0