wl18xx: add some boot operations and hw-specific configurations
Implement the boot operation. Add a wl18xx-specific configuration structure (namely to configure the mac and phy parameters). The default hw configuration matches the DVP board. Signed-off-by: Luciano Coelho <coelho@ti.com> Signed-off-by: Arik Nemtsov <arik@wizery.com>
This commit is contained in:
Luciano Coelho
parent
0cd6543f68
commit
46a1d51261
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@ -0,0 +1,57 @@
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/*
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* This file is part of wl18xx
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*
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* Copyright (C) 2011 Texas Instruments Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
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* 02110-1301 USA
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*
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*/
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#ifndef __WL18XX_CONF_H__
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#define __WL18XX_CONF_H__
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struct wl18xx_conf_phy {
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u8 phy_standalone;
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u8 rdl;
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u8 enable_clpc;
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u8 enable_tx_low_pwr_on_siso_rdl;
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u8 auto_detect;
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u8 dedicated_fem;
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u8 low_band_component;
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u8 low_band_component_type;
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u8 high_band_component;
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u8 high_band_component_type;
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u8 number_of_assembled_ant2_4;
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u8 number_of_assembled_ant5;
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u8 external_pa_dc2dc;
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u8 tcxo_ldo_voltage;
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u8 xtal_itrim_val;
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u8 srf_state;
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u8 io_configuration;
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u8 sdio_configuration;
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u8 settings;
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u8 rx_profile;
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u8 primary_clock_setting_time;
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u8 clock_valid_on_wake_up;
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u8 secondary_clock_setting_time;
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};
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struct wl18xx_conf {
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/* TODO: move the wlcore conf here? */
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struct wl18xx_conf_phy phy;
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};
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#endif /* __WL18XX_CONF_H__ */
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@ -24,8 +24,40 @@
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#include "../wlcore/wlcore.h"
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#include "../wlcore/debug.h"
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#include "../wlcore/io.h"
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#include "../wlcore/acx.h"
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#include "../wlcore/boot.h"
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#include "reg.h"
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#include "conf.h"
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static struct wl18xx_conf wl18xx_default_conf = {
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.phy = {
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.phy_standalone = 0x00,
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.primary_clock_setting_time = 0x05,
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.clock_valid_on_wake_up = 0x00,
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.secondary_clock_setting_time = 0x05,
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.rdl = 0x01,
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.auto_detect = 0x00,
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.dedicated_fem = FEM_NONE,
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.low_band_component = COMPONENT_2_WAY_SWITCH,
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.low_band_component_type = 0x05,
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.high_band_component = COMPONENT_2_WAY_SWITCH,
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.high_band_component_type = 0x09,
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.number_of_assembled_ant2_4 = 0x01,
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.number_of_assembled_ant5 = 0x01,
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.external_pa_dc2dc = 0x00,
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.tcxo_ldo_voltage = 0x00,
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.xtal_itrim_val = 0x04,
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.srf_state = 0x00,
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.io_configuration = 0x01,
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.sdio_configuration = 0x00,
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.settings = 0x00,
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.enable_clpc = 0x00,
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.enable_tx_low_pwr_on_siso_rdl = 0x00,
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.rx_profile = 0x00,
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},
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};
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static const struct wlcore_partition_set wl18xx_ptable[PART_TABLE_LEN] = {
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[PART_TOP_PRCM_ELP_SOC] = {
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@ -107,8 +139,154 @@ out:
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return ret;
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}
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static void wl18xx_set_clk(struct wl1271 *wl)
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{
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/*
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* TODO: this is hardcoded just for DVP/EVB, fix according to
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* new unified_drv.
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*/
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wl1271_write32(wl, WL18XX_SCR_PAD2, 0xB3);
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wlcore_set_partition(wl, &wl->ptable[PART_TOP_PRCM_ELP_SOC]);
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wl1271_write32(wl, 0x00A02360, 0xD0078);
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wl1271_write32(wl, 0x00A0236c, 0x12);
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wl1271_write32(wl, 0x00A02390, 0x20118);
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}
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static void wl18xx_boot_soft_reset(struct wl1271 *wl)
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{
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/* disable Rx/Tx */
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wl1271_write32(wl, WL18XX_ENABLE, 0x0);
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/* disable auto calibration on start*/
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wl1271_write32(wl, WL18XX_SPARE_A2, 0xffff);
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}
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static int wl18xx_pre_boot(struct wl1271 *wl)
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{
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/* TODO: add hw_pg_ver reading */
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wl18xx_set_clk(wl);
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/* Continue the ELP wake up sequence */
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wl1271_write32(wl, WL18XX_WELP_ARM_COMMAND, WELP_ARM_COMMAND_VAL);
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udelay(500);
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wlcore_set_partition(wl, &wl->ptable[PART_BOOT]);
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/* Disable interrupts */
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wlcore_write_reg(wl, REG_INTERRUPT_MASK, WL1271_ACX_INTR_ALL);
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wl18xx_boot_soft_reset(wl);
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return 0;
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}
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static void wl18xx_pre_upload(struct wl1271 *wl)
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{
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u32 tmp;
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wlcore_set_partition(wl, &wl->ptable[PART_BOOT]);
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/* TODO: check if this is all needed */
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wl1271_write32(wl, WL18XX_EEPROMLESS_IND, WL18XX_EEPROMLESS_IND);
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tmp = wlcore_read_reg(wl, REG_CHIP_ID_B);
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wl1271_debug(DEBUG_BOOT, "chip id 0x%x", tmp);
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tmp = wl1271_read32(wl, WL18XX_SCR_PAD2);
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}
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static void wl18xx_set_mac_and_phy(struct wl1271 *wl)
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{
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struct wl18xx_mac_and_phy_params params;
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memset(¶ms, 0, sizeof(params));
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params.phy_standalone = wl18xx_default_conf.phy.phy_standalone;
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params.rdl = wl18xx_default_conf.phy.rdl;
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params.enable_clpc = wl18xx_default_conf.phy.enable_clpc;
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params.enable_tx_low_pwr_on_siso_rdl =
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wl18xx_default_conf.phy.enable_tx_low_pwr_on_siso_rdl;
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params.auto_detect = wl18xx_default_conf.phy.auto_detect;
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params.dedicated_fem = wl18xx_default_conf.phy.dedicated_fem;
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params.low_band_component = wl18xx_default_conf.phy.low_band_component;
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params.low_band_component_type =
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wl18xx_default_conf.phy.low_band_component_type;
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params.high_band_component =
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wl18xx_default_conf.phy.high_band_component;
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params.high_band_component_type =
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wl18xx_default_conf.phy.high_band_component_type;
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params.number_of_assembled_ant2_4 =
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wl18xx_default_conf.phy.number_of_assembled_ant2_4;
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params.number_of_assembled_ant5 =
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wl18xx_default_conf.phy.number_of_assembled_ant5;
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params.external_pa_dc2dc = wl18xx_default_conf.phy.external_pa_dc2dc;
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params.tcxo_ldo_voltage = wl18xx_default_conf.phy.tcxo_ldo_voltage;
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params.xtal_itrim_val = wl18xx_default_conf.phy.xtal_itrim_val;
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params.srf_state = wl18xx_default_conf.phy.srf_state;
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params.io_configuration = wl18xx_default_conf.phy.io_configuration;
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params.sdio_configuration = wl18xx_default_conf.phy.sdio_configuration;
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params.settings = wl18xx_default_conf.phy.settings;
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params.rx_profile = wl18xx_default_conf.phy.rx_profile;
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params.primary_clock_setting_time =
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wl18xx_default_conf.phy.primary_clock_setting_time;
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params.clock_valid_on_wake_up =
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wl18xx_default_conf.phy.clock_valid_on_wake_up;
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params.secondary_clock_setting_time =
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wl18xx_default_conf.phy.secondary_clock_setting_time;
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/* TODO: hardcoded for now */
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params.board_type = BOARD_TYPE_DVP_EVB_18XX;
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wlcore_set_partition(wl, &wl->ptable[PART_PHY_INIT]);
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wl1271_write(wl, WL18XX_PHY_INIT_MEM_ADDR, (u8 *)¶ms,
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sizeof(params), false);
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}
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static void wl18xx_enable_interrupts(struct wl1271 *wl)
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{
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wlcore_write_reg(wl, REG_INTERRUPT_MASK, WL1271_ACX_ALL_EVENTS_VECTOR);
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wlcore_enable_interrupts(wl);
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wlcore_write_reg(wl, REG_INTERRUPT_MASK,
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WL1271_ACX_INTR_ALL & ~(WL1271_INTR_MASK));
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}
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static int wl18xx_boot(struct wl1271 *wl)
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{
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int ret;
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ret = wl18xx_pre_boot(wl);
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if (ret < 0)
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goto out;
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ret = wlcore_boot_upload_nvs(wl);
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if (ret < 0)
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goto out;
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wl18xx_pre_upload(wl);
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ret = wlcore_boot_upload_firmware(wl);
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if (ret < 0)
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goto out;
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wl18xx_set_mac_and_phy(wl);
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ret = wlcore_boot_run_firmware(wl);
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if (ret < 0)
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goto out;
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wl18xx_enable_interrupts(wl);
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out:
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return ret;
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}
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static struct wlcore_ops wl18xx_ops = {
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.identify_chip = wl18xx_identify_chip,
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.identify_chip = wl18xx_identify_chip,
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.boot = wl18xx_boot,
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};
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int __devinit wl18xx_probe(struct platform_device *pdev)
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@ -102,6 +102,10 @@
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#define WL18XX_REG_COMMAND_MAILBOX_PTR (WL18XX_SCR_PAD0)
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#define WL18XX_REG_EVENT_MAILBOX_PTR (WL18XX_SCR_PAD1)
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#define WL18XX_EEPROMLESS_IND (WL18XX_SCR_PAD4)
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#define WL18XX_WELP_ARM_COMMAND (WL18XX_REGISTERS_BASE + 0x7100)
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#define WL18XX_ENABLE (WL18XX_REGISTERS_BASE + 0x01543C)
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#define WL18XX_CMD_MBOX_ADDRESS 0xB007B4
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@ -109,4 +113,75 @@
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#define CHIP_ID_185x_PG10 (0x06030101)
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/* TODO: maybe move elsewhere? */
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#define NUM_OF_CHANNELS_11_ABG 150
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#define NUM_OF_CHANNELS_11_P 7
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#define WL18XX_NUM_OF_SUB_BANDS 9
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#define SRF_TABLE_LEN 16
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#define PIN_MUXING_SIZE 2
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enum {
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COMPONENT_NO_SWITCH = 0x0,
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COMPONENT_2_WAY_SWITCH = 0x1,
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COMPONENT_3_WAY_SWITCH = 0x2,
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COMPONENT_MATCHING = 0x3,
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};
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enum {
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FEM_NONE = 0x0,
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FEM_VENDOR_1 = 0x1,
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FEM_VENDOR_2 = 0x2,
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FEM_VENDOR_3 = 0x3,
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};
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enum {
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BOARD_TYPE_FPGA_18XX = 0,
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BOARD_TYPE_HDK_18XX = 1,
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BOARD_TYPE_DVP_EVB_18XX = 2,
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};
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struct wl18xx_mac_and_phy_params {
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u8 phy_standalone;
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u8 rdl;
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u8 enable_clpc;
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u8 enable_tx_low_pwr_on_siso_rdl;
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u8 auto_detect;
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u8 dedicated_fem;
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u8 low_band_component;
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/* Bit 0: One Hot, Bit 1: Control Enable, Bit 2: 1.8V, Bit 3: 3V */
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u8 low_band_component_type;
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u8 high_band_component;
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/* Bit 0: One Hot, Bit 1: Control Enable, Bit 2: 1.8V, Bit 3: 3V */
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u8 high_band_component_type;
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u8 number_of_assembled_ant2_4;
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u8 number_of_assembled_ant5;
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u8 pin_muxing_platform_options[PIN_MUXING_SIZE];
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u8 external_pa_dc2dc;
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u8 tcxo_ldo_voltage;
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u8 xtal_itrim_val;
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u8 srf_state;
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u8 srf1[SRF_TABLE_LEN];
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u8 srf2[SRF_TABLE_LEN];
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u8 srf3[SRF_TABLE_LEN];
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u8 io_configuration;
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u8 sdio_configuration;
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u8 settings;
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u8 rx_profile;
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u8 per_chan_pwr_limit_arr_11abg[NUM_OF_CHANNELS_11_ABG];
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u8 pwr_limit_reference_11_abg;
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u8 per_chan_pwr_limit_arr_11p[NUM_OF_CHANNELS_11_P];
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u8 pwr_limit_reference_11p;
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u8 per_sub_band_tx_trace_loss[WL18XX_NUM_OF_SUB_BANDS];
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u8 per_sub_band_rx_trace_loss[WL18XX_NUM_OF_SUB_BANDS];
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u8 primary_clock_setting_time;
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u8 clock_valid_on_wake_up;
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u8 secondary_clock_setting_time;
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u8 board_type;
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u8 padding[1];
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} __packed;
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#endif /* __REG_H__ */
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