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drm/i915/cnl; Add macro to get PORT_TX register 

This patch creates a new macro to get PORT_TX register for any given DW.
This removes the need of defining register address for each port & DW.

Changes since V1:
 - Use underscope prefix, as macro isn't returning an mmio reg(Lucas)
 - Merge patch 1 & 2 of the series
Changes since V2:
 - remove _MMIO_PORT6_LN macro (Rodrigo)

Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180314080653.9444-2-mahesh1.kumar@intel.com
This commit is contained in:
Mahesh Kumar 2018-03-14 13:36:52 +05:30 committed by Rodrigo Vivi
parent ad055fb8e0
commit 4635b57363
1 changed files with 39 additions and 98 deletions
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137
drivers/gpu/drm/i915/i915_reg.h
View File

@ -154,8 +154,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define _PLL(pll, a, b) ((a) + (pll)*((b)-(a))) #define _PLL(pll, a, b) ((a) + (pll)*((b)-(a)))
#define _MMIO_PLL(pll, a, b) _MMIO(_PLL(pll, a, b)) #define _MMIO_PLL(pll, a, b) _MMIO(_PLL(pll, a, b))
#define _MMIO_PORT6(port, a, b, c, d, e, f) _MMIO(_PICK(port, a, b, c, d, e, f)) #define _MMIO_PORT6(port, a, b, c, d, e, f) _MMIO(_PICK(port, a, b, c, d, e, f))
#define _MMIO_PORT6_LN(port, ln, a0, a1, b, c, d, e, f) \
_MMIO(_PICK(port, a0, b, c, d, e, f) + (ln * (a1 - a0)))
#define _PHY3(phy, ...) _PICK(phy, __VA_ARGS__) #define _PHY3(phy, ...) _PICK(phy, __VA_ARGS__)
#define _MMIO_PHY3(phy, a, b, c) _MMIO(_PHY3(phy, a, b, c)) #define _MMIO_PHY3(phy, a, b, c) _MMIO(_PHY3(phy, a, b, c))
@ -1964,30 +1962,36 @@ enum i915_power_well_id {
_CNL_PORT_PCS_DW1_LN0_F) _CNL_PORT_PCS_DW1_LN0_F)
#define COMMON_KEEPER_EN (1 << 26) #define COMMON_KEEPER_EN (1 << 26)
#define _CNL_PORT_TX_DW2_GRP_AE 0x162348 /* CNL Port TX registers */
#define _CNL_PORT_TX_DW2_GRP_B 0x1623C8 #define _CNL_PORT_TX_AE_GRP_OFFSET 0x162340
#define _CNL_PORT_TX_DW2_GRP_C 0x162B48 #define _CNL_PORT_TX_B_GRP_OFFSET 0x1623C0
#define _CNL_PORT_TX_DW2_GRP_D 0x162BC8 #define _CNL_PORT_TX_C_GRP_OFFSET 0x162B40
#define _CNL_PORT_TX_DW2_GRP_F 0x162A48 #define _CNL_PORT_TX_D_GRP_OFFSET 0x162BC0
#define _CNL_PORT_TX_DW2_LN0_AE 0x162448 #define _CNL_PORT_TX_F_GRP_OFFSET 0x162A40
#define _CNL_PORT_TX_DW2_LN0_B 0x162648 #define _CNL_PORT_TX_AE_LN0_OFFSET 0x162440
#define _CNL_PORT_TX_DW2_LN0_C 0x162C48 #define _CNL_PORT_TX_B_LN0_OFFSET 0x162640
#define _CNL_PORT_TX_DW2_LN0_D 0x162E48 #define _CNL_PORT_TX_C_LN0_OFFSET 0x162C40
#define _CNL_PORT_TX_DW2_LN0_F 0x162848 #define _CNL_PORT_TX_D_LN0_OFFSET 0x162E40
#define CNL_PORT_TX_DW2_GRP(port) _MMIO_PORT6(port, \ #define _CNL_PORT_TX_F_LN0_OFFSET 0x162840
_CNL_PORT_TX_DW2_GRP_AE, \ #define _CNL_PORT_TX_DW_GRP(port, dw) (_PICK((port), \
_CNL_PORT_TX_DW2_GRP_B, \ _CNL_PORT_TX_AE_GRP_OFFSET, \
_CNL_PORT_TX_DW2_GRP_C, \ _CNL_PORT_TX_B_GRP_OFFSET, \
_CNL_PORT_TX_DW2_GRP_D, \ _CNL_PORT_TX_B_GRP_OFFSET, \
_CNL_PORT_TX_DW2_GRP_AE, \ _CNL_PORT_TX_D_GRP_OFFSET, \
_CNL_PORT_TX_DW2_GRP_F) _CNL_PORT_TX_AE_GRP_OFFSET, \
#define CNL_PORT_TX_DW2_LN0(port) _MMIO_PORT6(port, \ _CNL_PORT_TX_F_GRP_OFFSET) + \
_CNL_PORT_TX_DW2_LN0_AE, \ 4*(dw))
_CNL_PORT_TX_DW2_LN0_B, \ #define _CNL_PORT_TX_DW_LN0(port, dw) (_PICK((port), \
_CNL_PORT_TX_DW2_LN0_C, \ _CNL_PORT_TX_AE_LN0_OFFSET, \
_CNL_PORT_TX_DW2_LN0_D, \ _CNL_PORT_TX_B_LN0_OFFSET, \
_CNL_PORT_TX_DW2_LN0_AE, \ _CNL_PORT_TX_B_LN0_OFFSET, \
_CNL_PORT_TX_DW2_LN0_F) _CNL_PORT_TX_D_LN0_OFFSET, \
_CNL_PORT_TX_AE_LN0_OFFSET, \
_CNL_PORT_TX_F_LN0_OFFSET) + \
4*(dw))
#define CNL_PORT_TX_DW2_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP((port), 2))
#define CNL_PORT_TX_DW2_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0((port), 2))
#define SWING_SEL_UPPER(x) ((x >> 3) << 15) #define SWING_SEL_UPPER(x) ((x >> 3) << 15)
#define SWING_SEL_UPPER_MASK (1 << 15) #define SWING_SEL_UPPER_MASK (1 << 15)
#define SWING_SEL_LOWER(x) ((x & 0x7) << 11) #define SWING_SEL_LOWER(x) ((x & 0x7) << 11)
@ -1995,32 +1999,13 @@ enum i915_power_well_id {
#define RCOMP_SCALAR(x) ((x) << 0) #define RCOMP_SCALAR(x) ((x) << 0)
#define RCOMP_SCALAR_MASK (0xFF << 0) #define RCOMP_SCALAR_MASK (0xFF << 0)
#define _CNL_PORT_TX_DW4_GRP_AE 0x162350
#define _CNL_PORT_TX_DW4_GRP_B 0x1623D0
#define _CNL_PORT_TX_DW4_GRP_C 0x162B50
#define _CNL_PORT_TX_DW4_GRP_D 0x162BD0
#define _CNL_PORT_TX_DW4_GRP_F 0x162A50
#define _CNL_PORT_TX_DW4_LN0_AE 0x162450 #define _CNL_PORT_TX_DW4_LN0_AE 0x162450
#define _CNL_PORT_TX_DW4_LN1_AE 0x1624D0 #define _CNL_PORT_TX_DW4_LN1_AE 0x1624D0
#define _CNL_PORT_TX_DW4_LN0_B 0x162650 #define CNL_PORT_TX_DW4_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP((port), 4))
#define _CNL_PORT_TX_DW4_LN0_C 0x162C50 #define CNL_PORT_TX_DW4_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0((port), 4))
#define _CNL_PORT_TX_DW4_LN0_D 0x162E50 #define CNL_PORT_TX_DW4_LN(port, ln) _MMIO(_CNL_PORT_TX_DW_LN0((port), 4) + \
#define _CNL_PORT_TX_DW4_LN0_F 0x162850 (ln * (_CNL_PORT_TX_DW4_LN1_AE - \
#define CNL_PORT_TX_DW4_GRP(port) _MMIO_PORT6(port, \ _CNL_PORT_TX_DW4_LN0_AE)))
_CNL_PORT_TX_DW4_GRP_AE, \
_CNL_PORT_TX_DW4_GRP_B, \
_CNL_PORT_TX_DW4_GRP_C, \
_CNL_PORT_TX_DW4_GRP_D, \
_CNL_PORT_TX_DW4_GRP_AE, \
_CNL_PORT_TX_DW4_GRP_F)
#define CNL_PORT_TX_DW4_LN(port, ln) _MMIO_PORT6_LN(port, ln, \
_CNL_PORT_TX_DW4_LN0_AE, \
_CNL_PORT_TX_DW4_LN1_AE, \
_CNL_PORT_TX_DW4_LN0_B, \
_CNL_PORT_TX_DW4_LN0_C, \
_CNL_PORT_TX_DW4_LN0_D, \
_CNL_PORT_TX_DW4_LN0_AE, \
_CNL_PORT_TX_DW4_LN0_F)
#define LOADGEN_SELECT (1 << 31) #define LOADGEN_SELECT (1 << 31)
#define POST_CURSOR_1(x) ((x) << 12) #define POST_CURSOR_1(x) ((x) << 12)
#define POST_CURSOR_1_MASK (0x3F << 12) #define POST_CURSOR_1_MASK (0x3F << 12)
@ -2029,30 +2014,8 @@ enum i915_power_well_id {
#define CURSOR_COEFF(x) ((x) << 0) #define CURSOR_COEFF(x) ((x) << 0)
#define CURSOR_COEFF_MASK (0x3F << 0) #define CURSOR_COEFF_MASK (0x3F << 0)
#define _CNL_PORT_TX_DW5_GRP_AE 0x162354 #define CNL_PORT_TX_DW5_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP((port), 5))
#define _CNL_PORT_TX_DW5_GRP_B 0x1623D4 #define CNL_PORT_TX_DW5_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0((port), 5))
#define _CNL_PORT_TX_DW5_GRP_C 0x162B54
#define _CNL_PORT_TX_DW5_GRP_D 0x162BD4
#define _CNL_PORT_TX_DW5_GRP_F 0x162A54
#define _CNL_PORT_TX_DW5_LN0_AE 0x162454
#define _CNL_PORT_TX_DW5_LN0_B 0x162654
#define _CNL_PORT_TX_DW5_LN0_C 0x162C54
#define _CNL_PORT_TX_DW5_LN0_D 0x162E54
#define _CNL_PORT_TX_DW5_LN0_F 0x162854
#define CNL_PORT_TX_DW5_GRP(port) _MMIO_PORT6(port, \
_CNL_PORT_TX_DW5_GRP_AE, \
_CNL_PORT_TX_DW5_GRP_B, \
_CNL_PORT_TX_DW5_GRP_C, \
_CNL_PORT_TX_DW5_GRP_D, \
_CNL_PORT_TX_DW5_GRP_AE, \
_CNL_PORT_TX_DW5_GRP_F)
#define CNL_PORT_TX_DW5_LN0(port) _MMIO_PORT6(port, \
_CNL_PORT_TX_DW5_LN0_AE, \
_CNL_PORT_TX_DW5_LN0_B, \
_CNL_PORT_TX_DW5_LN0_C, \
_CNL_PORT_TX_DW5_LN0_D, \
_CNL_PORT_TX_DW5_LN0_AE, \
_CNL_PORT_TX_DW5_LN0_F)
#define TX_TRAINING_EN (1 << 31) #define TX_TRAINING_EN (1 << 31)
#define TAP3_DISABLE (1 << 29) #define TAP3_DISABLE (1 << 29)
#define SCALING_MODE_SEL(x) ((x) << 18) #define SCALING_MODE_SEL(x) ((x) << 18)
@ -2060,30 +2023,8 @@ enum i915_power_well_id {
#define RTERM_SELECT(x) ((x) << 3) #define RTERM_SELECT(x) ((x) << 3)
#define RTERM_SELECT_MASK (0x7 << 3) #define RTERM_SELECT_MASK (0x7 << 3)
#define _CNL_PORT_TX_DW7_GRP_AE 0x16235C #define CNL_PORT_TX_DW7_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP((port), 7))
#define _CNL_PORT_TX_DW7_GRP_B 0x1623DC #define CNL_PORT_TX_DW7_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0((port), 7))
#define _CNL_PORT_TX_DW7_GRP_C 0x162B5C
#define _CNL_PORT_TX_DW7_GRP_D 0x162BDC
#define _CNL_PORT_TX_DW7_GRP_F 0x162A5C
#define _CNL_PORT_TX_DW7_LN0_AE 0x16245C
#define _CNL_PORT_TX_DW7_LN0_B 0x16265C
#define _CNL_PORT_TX_DW7_LN0_C 0x162C5C
#define _CNL_PORT_TX_DW7_LN0_D 0x162E5C
#define _CNL_PORT_TX_DW7_LN0_F 0x16285C
#define CNL_PORT_TX_DW7_GRP(port) _MMIO_PORT6(port, \
_CNL_PORT_TX_DW7_GRP_AE, \
_CNL_PORT_TX_DW7_GRP_B, \
_CNL_PORT_TX_DW7_GRP_C, \
_CNL_PORT_TX_DW7_GRP_D, \
_CNL_PORT_TX_DW7_GRP_AE, \
_CNL_PORT_TX_DW7_GRP_F)
#define CNL_PORT_TX_DW7_LN0(port) _MMIO_PORT6(port, \
_CNL_PORT_TX_DW7_LN0_AE, \
_CNL_PORT_TX_DW7_LN0_B, \
_CNL_PORT_TX_DW7_LN0_C, \
_CNL_PORT_TX_DW7_LN0_D, \
_CNL_PORT_TX_DW7_LN0_AE, \
_CNL_PORT_TX_DW7_LN0_F)
#define N_SCALAR(x) ((x) << 24) #define N_SCALAR(x) ((x) << 24)
#define N_SCALAR_MASK (0x7F << 24) #define N_SCALAR_MASK (0x7F << 24)