drm/i915/cnl; Add macro to get PORT_TX register
This patch creates a new macro to get PORT_TX register for any given DW. This removes the need of defining register address for each port & DW. Changes since V1: - Use underscope prefix, as macro isn't returning an mmio reg(Lucas) - Merge patch 1 & 2 of the series Changes since V2: - remove _MMIO_PORT6_LN macro (Rodrigo) Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180314080653.9444-2-mahesh1.kumar@intel.com
This commit is contained in:
Mahesh Kumar
Rodrigo Vivi
parent
ad055fb8e0
commit
4635b57363
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@ -154,8 +154,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
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#define _PLL(pll, a, b) ((a) + (pll)*((b)-(a)))
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#define _MMIO_PLL(pll, a, b) _MMIO(_PLL(pll, a, b))
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#define _MMIO_PORT6(port, a, b, c, d, e, f) _MMIO(_PICK(port, a, b, c, d, e, f))
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#define _MMIO_PORT6_LN(port, ln, a0, a1, b, c, d, e, f) \
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_MMIO(_PICK(port, a0, b, c, d, e, f) + (ln * (a1 - a0)))
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#define _PHY3(phy, ...) _PICK(phy, __VA_ARGS__)
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#define _MMIO_PHY3(phy, a, b, c) _MMIO(_PHY3(phy, a, b, c))
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@ -1964,30 +1962,36 @@ enum i915_power_well_id {
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_CNL_PORT_PCS_DW1_LN0_F)
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#define COMMON_KEEPER_EN (1 << 26)
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#define _CNL_PORT_TX_DW2_GRP_AE 0x162348
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#define _CNL_PORT_TX_DW2_GRP_B 0x1623C8
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#define _CNL_PORT_TX_DW2_GRP_C 0x162B48
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#define _CNL_PORT_TX_DW2_GRP_D 0x162BC8
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#define _CNL_PORT_TX_DW2_GRP_F 0x162A48
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#define _CNL_PORT_TX_DW2_LN0_AE 0x162448
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#define _CNL_PORT_TX_DW2_LN0_B 0x162648
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#define _CNL_PORT_TX_DW2_LN0_C 0x162C48
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#define _CNL_PORT_TX_DW2_LN0_D 0x162E48
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#define _CNL_PORT_TX_DW2_LN0_F 0x162848
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#define CNL_PORT_TX_DW2_GRP(port) _MMIO_PORT6(port, \
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_CNL_PORT_TX_DW2_GRP_AE, \
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_CNL_PORT_TX_DW2_GRP_B, \
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_CNL_PORT_TX_DW2_GRP_C, \
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_CNL_PORT_TX_DW2_GRP_D, \
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_CNL_PORT_TX_DW2_GRP_AE, \
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_CNL_PORT_TX_DW2_GRP_F)
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#define CNL_PORT_TX_DW2_LN0(port) _MMIO_PORT6(port, \
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_CNL_PORT_TX_DW2_LN0_AE, \
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_CNL_PORT_TX_DW2_LN0_B, \
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_CNL_PORT_TX_DW2_LN0_C, \
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_CNL_PORT_TX_DW2_LN0_D, \
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_CNL_PORT_TX_DW2_LN0_AE, \
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_CNL_PORT_TX_DW2_LN0_F)
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/* CNL Port TX registers */
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#define _CNL_PORT_TX_AE_GRP_OFFSET 0x162340
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#define _CNL_PORT_TX_B_GRP_OFFSET 0x1623C0
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#define _CNL_PORT_TX_C_GRP_OFFSET 0x162B40
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#define _CNL_PORT_TX_D_GRP_OFFSET 0x162BC0
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#define _CNL_PORT_TX_F_GRP_OFFSET 0x162A40
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#define _CNL_PORT_TX_AE_LN0_OFFSET 0x162440
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#define _CNL_PORT_TX_B_LN0_OFFSET 0x162640
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#define _CNL_PORT_TX_C_LN0_OFFSET 0x162C40
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#define _CNL_PORT_TX_D_LN0_OFFSET 0x162E40
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#define _CNL_PORT_TX_F_LN0_OFFSET 0x162840
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#define _CNL_PORT_TX_DW_GRP(port, dw) (_PICK((port), \
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_CNL_PORT_TX_AE_GRP_OFFSET, \
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_CNL_PORT_TX_B_GRP_OFFSET, \
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_CNL_PORT_TX_B_GRP_OFFSET, \
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_CNL_PORT_TX_D_GRP_OFFSET, \
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_CNL_PORT_TX_AE_GRP_OFFSET, \
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_CNL_PORT_TX_F_GRP_OFFSET) + \
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4*(dw))
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#define _CNL_PORT_TX_DW_LN0(port, dw) (_PICK((port), \
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_CNL_PORT_TX_AE_LN0_OFFSET, \
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_CNL_PORT_TX_B_LN0_OFFSET, \
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_CNL_PORT_TX_B_LN0_OFFSET, \
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_CNL_PORT_TX_D_LN0_OFFSET, \
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_CNL_PORT_TX_AE_LN0_OFFSET, \
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_CNL_PORT_TX_F_LN0_OFFSET) + \
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4*(dw))
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#define CNL_PORT_TX_DW2_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP((port), 2))
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#define CNL_PORT_TX_DW2_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0((port), 2))
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#define SWING_SEL_UPPER(x) ((x >> 3) << 15)
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#define SWING_SEL_UPPER_MASK (1 << 15)
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#define SWING_SEL_LOWER(x) ((x & 0x7) << 11)
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@ -1995,32 +1999,13 @@ enum i915_power_well_id {
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#define RCOMP_SCALAR(x) ((x) << 0)
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#define RCOMP_SCALAR_MASK (0xFF << 0)
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#define _CNL_PORT_TX_DW4_GRP_AE 0x162350
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#define _CNL_PORT_TX_DW4_GRP_B 0x1623D0
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#define _CNL_PORT_TX_DW4_GRP_C 0x162B50
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#define _CNL_PORT_TX_DW4_GRP_D 0x162BD0
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#define _CNL_PORT_TX_DW4_GRP_F 0x162A50
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#define _CNL_PORT_TX_DW4_LN0_AE 0x162450
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#define _CNL_PORT_TX_DW4_LN1_AE 0x1624D0
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#define _CNL_PORT_TX_DW4_LN0_B 0x162650
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#define _CNL_PORT_TX_DW4_LN0_C 0x162C50
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#define _CNL_PORT_TX_DW4_LN0_D 0x162E50
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#define _CNL_PORT_TX_DW4_LN0_F 0x162850
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#define CNL_PORT_TX_DW4_GRP(port) _MMIO_PORT6(port, \
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_CNL_PORT_TX_DW4_GRP_AE, \
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_CNL_PORT_TX_DW4_GRP_B, \
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_CNL_PORT_TX_DW4_GRP_C, \
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_CNL_PORT_TX_DW4_GRP_D, \
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_CNL_PORT_TX_DW4_GRP_AE, \
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_CNL_PORT_TX_DW4_GRP_F)
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#define CNL_PORT_TX_DW4_LN(port, ln) _MMIO_PORT6_LN(port, ln, \
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_CNL_PORT_TX_DW4_LN0_AE, \
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_CNL_PORT_TX_DW4_LN1_AE, \
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_CNL_PORT_TX_DW4_LN0_B, \
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_CNL_PORT_TX_DW4_LN0_C, \
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_CNL_PORT_TX_DW4_LN0_D, \
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_CNL_PORT_TX_DW4_LN0_AE, \
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_CNL_PORT_TX_DW4_LN0_F)
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#define CNL_PORT_TX_DW4_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP((port), 4))
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#define CNL_PORT_TX_DW4_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0((port), 4))
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#define CNL_PORT_TX_DW4_LN(port, ln) _MMIO(_CNL_PORT_TX_DW_LN0((port), 4) + \
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(ln * (_CNL_PORT_TX_DW4_LN1_AE - \
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_CNL_PORT_TX_DW4_LN0_AE)))
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#define LOADGEN_SELECT (1 << 31)
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#define POST_CURSOR_1(x) ((x) << 12)
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#define POST_CURSOR_1_MASK (0x3F << 12)
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@ -2029,30 +2014,8 @@ enum i915_power_well_id {
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#define CURSOR_COEFF(x) ((x) << 0)
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#define CURSOR_COEFF_MASK (0x3F << 0)
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#define _CNL_PORT_TX_DW5_GRP_AE 0x162354
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#define _CNL_PORT_TX_DW5_GRP_B 0x1623D4
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#define _CNL_PORT_TX_DW5_GRP_C 0x162B54
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#define _CNL_PORT_TX_DW5_GRP_D 0x162BD4
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#define _CNL_PORT_TX_DW5_GRP_F 0x162A54
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#define _CNL_PORT_TX_DW5_LN0_AE 0x162454
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#define _CNL_PORT_TX_DW5_LN0_B 0x162654
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#define _CNL_PORT_TX_DW5_LN0_C 0x162C54
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#define _CNL_PORT_TX_DW5_LN0_D 0x162E54
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#define _CNL_PORT_TX_DW5_LN0_F 0x162854
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#define CNL_PORT_TX_DW5_GRP(port) _MMIO_PORT6(port, \
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_CNL_PORT_TX_DW5_GRP_AE, \
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_CNL_PORT_TX_DW5_GRP_B, \
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_CNL_PORT_TX_DW5_GRP_C, \
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_CNL_PORT_TX_DW5_GRP_D, \
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_CNL_PORT_TX_DW5_GRP_AE, \
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_CNL_PORT_TX_DW5_GRP_F)
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#define CNL_PORT_TX_DW5_LN0(port) _MMIO_PORT6(port, \
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_CNL_PORT_TX_DW5_LN0_AE, \
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_CNL_PORT_TX_DW5_LN0_B, \
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_CNL_PORT_TX_DW5_LN0_C, \
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_CNL_PORT_TX_DW5_LN0_D, \
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_CNL_PORT_TX_DW5_LN0_AE, \
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_CNL_PORT_TX_DW5_LN0_F)
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#define CNL_PORT_TX_DW5_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP((port), 5))
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#define CNL_PORT_TX_DW5_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0((port), 5))
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#define TX_TRAINING_EN (1 << 31)
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#define TAP3_DISABLE (1 << 29)
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#define SCALING_MODE_SEL(x) ((x) << 18)
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@ -2060,30 +2023,8 @@ enum i915_power_well_id {
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#define RTERM_SELECT(x) ((x) << 3)
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#define RTERM_SELECT_MASK (0x7 << 3)
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#define _CNL_PORT_TX_DW7_GRP_AE 0x16235C
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#define _CNL_PORT_TX_DW7_GRP_B 0x1623DC
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#define _CNL_PORT_TX_DW7_GRP_C 0x162B5C
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#define _CNL_PORT_TX_DW7_GRP_D 0x162BDC
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#define _CNL_PORT_TX_DW7_GRP_F 0x162A5C
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#define _CNL_PORT_TX_DW7_LN0_AE 0x16245C
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#define _CNL_PORT_TX_DW7_LN0_B 0x16265C
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#define _CNL_PORT_TX_DW7_LN0_C 0x162C5C
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#define _CNL_PORT_TX_DW7_LN0_D 0x162E5C
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#define _CNL_PORT_TX_DW7_LN0_F 0x16285C
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#define CNL_PORT_TX_DW7_GRP(port) _MMIO_PORT6(port, \
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_CNL_PORT_TX_DW7_GRP_AE, \
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_CNL_PORT_TX_DW7_GRP_B, \
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_CNL_PORT_TX_DW7_GRP_C, \
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_CNL_PORT_TX_DW7_GRP_D, \
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_CNL_PORT_TX_DW7_GRP_AE, \
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_CNL_PORT_TX_DW7_GRP_F)
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#define CNL_PORT_TX_DW7_LN0(port) _MMIO_PORT6(port, \
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_CNL_PORT_TX_DW7_LN0_AE, \
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_CNL_PORT_TX_DW7_LN0_B, \
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_CNL_PORT_TX_DW7_LN0_C, \
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_CNL_PORT_TX_DW7_LN0_D, \
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_CNL_PORT_TX_DW7_LN0_AE, \
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_CNL_PORT_TX_DW7_LN0_F)
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#define CNL_PORT_TX_DW7_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP((port), 7))
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#define CNL_PORT_TX_DW7_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0((port), 7))
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#define N_SCALAR(x) ((x) << 24)
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#define N_SCALAR_MASK (0x7F << 24)
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