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Samsung 2nd drivers for 3.16 

This is including fix exynos cpufreq driver compilation with
 ARCH_MULTIPLATFORM. Even though this is a work around, this
 is required for support exynos multiplatform for a while and
 will be updated in near future.
 
 This is based on tags/samsung-exynos.
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Merge tag 'samsung-drivers-2' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/drivers

Merge "Samsung 2nd drivers for 3.16" from Kukjin Kim:

This is including fix exynos cpufreq driver compilation with
ARCH_MULTIPLATFORM. Even though this is a work around, this
is required for support exynos multiplatform for a while and
will be updated in near future.

This is based on tags/samsung-exynos.

* tag 'samsung-drivers-2' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: (24 commits)
  cpufreq: exynos: Fix driver compilation with ARCH_MULTIPLATFORM
  ARM: EXYNOS: Enable multi-platform build support
  ARM: EXYNOS: Consolidate Kconfig entries
  ARM: EXYNOS: Add support for EXYNOS5410 SoC
  ARM: EXYNOS: Support secondary CPU boot of Exynos3250
  ARM: EXYNOS: Add Exynos3250 SoC ID
  ARM: EXYNOS: Add 5800 SoC support
  ARM: EXYNOS: initial board support for exynos5260 SoC
  clk: exynos5250: Add missing sysmmu clocks for DISP and ISP blocks
  cpufreq: exynos: Fix the compile error
  ARM: S3C24XX: move debug-macro.S into the common space
  ARM: S3C24XX: use generic DEBUG_UART_PHY/_VIRT in debug macro
  ARM: S3C24XX: trim down debug uart handling
  ARM: compressed/head.S: remove s3c24xx special case
  ARM: EXYNOS: Remove unnecessary inclusion of cpu.h
  ARM: EXYNOS: Migrate Exynos specific macros from plat to mach
  ARM: EXYNOS: Remove exynos_subsys registration
  ARM: EXYNOS: Remove duplicate lines in Makefile
  ARM: EXYNOS: use v7_exit_coherency_flush macro for cache disabling
  ARM: dts: Remove g2d_pd node for exynos5420
  ...

Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2014-05-30 21:48:39 -07:00
parent b5de1ce01a 4c8d819343
commit 45e70b7d48
28 changed files with 481 additions and 423 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

20
arch/arm/Kconfig
View File

@ -829,26 +829,6 @@ config ARCH_S5PV210
help
Samsung S5PV210/S5PC110 series based systems
config ARCH_EXYNOS
bool "Samsung EXYNOS"
select ARCH_HAS_CPUFREQ
select ARCH_HAS_HOLES_MEMORYMODEL
select ARCH_REQUIRE_GPIOLIB
select ARCH_SPARSEMEM_ENABLE
select ARM_GIC
select COMMON_CLK_SAMSUNG
select CPU_V7
select GENERIC_CLOCKEVENTS
select HAVE_S3C2410_I2C if I2C
select HAVE_S3C2410_WATCHDOG if WATCHDOG
select HAVE_S3C_RTC if RTC_CLASS
select NEED_MACH_MEMORY_H
select SPARSE_IRQ
select SRAM
select USE_OF
help
Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
config ARCH_DAVINCI
bool "TI DaVinci"
select ARCH_HAS_HOLES_MEMORYMODEL

54
arch/arm/Kconfig.debug
View File

@ -625,6 +625,7 @@ choice
config DEBUG_S3C_UART0
depends on PLAT_SAMSUNG
select DEBUG_EXYNOS_UART if ARCH_EXYNOS
select DEBUG_S3C24XX_UART if ARCH_S3C24XX
bool "Use S3C UART 0 for low-level debug"
help
Say Y here if you want the debug print routines to direct
@ -637,6 +638,7 @@ choice
config DEBUG_S3C_UART1
depends on PLAT_SAMSUNG
select DEBUG_EXYNOS_UART if ARCH_EXYNOS
select DEBUG_S3C24XX_UART if ARCH_S3C24XX
bool "Use S3C UART 1 for low-level debug"
help
Say Y here if you want the debug print routines to direct
@ -649,6 +651,7 @@ choice
config DEBUG_S3C_UART2
depends on PLAT_SAMSUNG
select DEBUG_EXYNOS_UART if ARCH_EXYNOS
select DEBUG_S3C24XX_UART if ARCH_S3C24XX
bool "Use S3C UART 2 for low-level debug"
help
Say Y here if you want the debug print routines to direct
@ -670,6 +673,33 @@ choice
The uncompressor code port configuration is now handled
by CONFIG_S3C_LOWLEVEL_UART_PORT.
config DEBUG_S3C2410_UART0
depends on ARCH_S3C24XX
select DEBUG_S3C2410_UART
bool "Use S3C2410/S3C2412 UART 0 for low-level debug"
help
Say Y here if you want the debug print routines to direct
their output to UART 0. The port must have been initialised
by the boot-loader before use.
config DEBUG_S3C2410_UART1
depends on ARCH_S3C24XX
select DEBUG_S3C2410_UART
bool "Use S3C2410/S3C2412 UART 1 for low-level debug"
help
Say Y here if you want the debug print routines to direct
their output to UART 1. The port must have been initialised
by the boot-loader before use.
config DEBUG_S3C2410_UART2
depends on ARCH_S3C24XX
select DEBUG_S3C2410_UART
bool "Use S3C2410/S3C2412 UART 2 for low-level debug"
help
Say Y here if you want the debug print routines to direct
their output to UART 2. The port must have been initialised
by the boot-loader before use.
config DEBUG_SOCFPGA_UART
depends on ARCH_SOCFPGA
bool "Use SOCFPGA UART for low-level debug"
@ -921,6 +951,13 @@ endchoice
config DEBUG_EXYNOS_UART
bool
config DEBUG_S3C2410_UART
bool
select DEBUG_S3C24XX_UART
config DEBUG_S3C24XX_UART
bool
config DEBUG_OMAP2PLUS_UART
bool
depends on ARCH_OMAP2PLUS
@ -973,6 +1010,7 @@ config DEBUG_LL_INCLUDE
DEBUG_IMX6SL_UART
default "debug/msm.S" if DEBUG_MSM_UART
default "debug/omap2plus.S" if DEBUG_OMAP2PLUS_UART
default "debug/s3c24xx.S" if DEBUG_S3C24XX_UART
default "debug/sirf.S" if DEBUG_SIRFPRIMA2_UART1 || DEBUG_SIRFMARCO_UART1
default "debug/sti.S" if DEBUG_STI_UART
default "debug/tegra.S" if DEBUG_TEGRA_UART
@ -1029,6 +1067,12 @@ config DEBUG_UART_PHYS
default 0x40090000 if ARCH_LPC32XX
default 0x40100000 if DEBUG_PXA_UART1
default 0x42000000 if ARCH_GEMINI
default 0x50000000 if DEBUG_S3C24XX_UART && (DEBUG_S3C_UART0 || \
DEBUG_S3C2410_UART0)
default 0x50004000 if DEBUG_S3C24XX_UART && (DEBUG_S3C_UART1 || \
DEBUG_S3C2410_UART1)
default 0x50008000 if DEBUG_S3C24XX_UART && (DEBUG_S3C_UART2 || \
DEBUG_S3C2410_UART2)
default 0x7c0003f8 if FOOTBRIDGE
default 0x80070000 if DEBUG_IMX23_UART
default 0x80074000 if DEBUG_IMX28_UART
@ -1058,7 +1102,7 @@ config DEBUG_UART_PHYS
default 0xfffff700 if ARCH_IOP33X
depends on DEBUG_LL_UART_8250 || DEBUG_LL_UART_PL01X || \
DEBUG_LL_UART_EFM32 || \
DEBUG_UART_8250 || DEBUG_UART_PL01X
DEBUG_UART_8250 || DEBUG_UART_PL01X || DEBUG_S3C24XX_UART
config DEBUG_UART_VIRT
hex "Virtual base address of debug UART"
@ -1075,6 +1119,12 @@ config DEBUG_UART_VIRT
default 0xf2100000 if DEBUG_PXA_UART1
default 0xf4090000 if ARCH_LPC32XX
default 0xf4200000 if ARCH_GEMINI
default 0xf7000000 if DEBUG_S3C24XX_UART && (DEBUG_S3C_UART0 || \
DEBUG_S3C2410_UART0)
default 0xf7004000 if DEBUG_S3C24XX_UART && (DEBUG_S3C_UART1 || \
DEBUG_S3C2410_UART1)
default 0xf7008000 if DEBUG_S3C24XX_UART && (DEBUG_S3C_UART2 || \
DEBUG_S3C2410_UART2)
default 0xf7fc9000 if DEBUG_BERLIN_UART
default 0xf8009000 if DEBUG_VEXPRESS_UART0_CA9
default 0xf8090000 if DEBUG_VEXPRESS_UART0_RS1
@ -1116,7 +1166,7 @@ config DEBUG_UART_VIRT
default 0xff003000 if DEBUG_U300_UART
default DEBUG_UART_PHYS if !MMU
depends on DEBUG_LL_UART_8250 || DEBUG_LL_UART_PL01X || \
DEBUG_UART_8250 || DEBUG_UART_PL01X
DEBUG_UART_8250 || DEBUG_UART_PL01X || DEBUG_S3C24XX_UART
config DEBUG_UART_8250_SHIFT
int "Register offset shift for the 8250 debug UART"

5
arch/arm/boot/compressed/head.S
View File

@ -60,11 +60,6 @@
add \rb, \rb, #0x00010000 @ Ser1
#endif
.endm
#elif defined(CONFIG_ARCH_S3C24XX)
.macro loadsp, rb, tmp
mov \rb, #0x50000000
add \rb, \rb, #0x4000 * CONFIG_S3C_LOWLEVEL_UART_PORT
.endm
#else
.macro loadsp, rb, tmp
addruart \rb, \tmp

12
arch/arm/boot/dts/exynos5420-arndale-octa.dts
View File

@ -364,16 +364,4 @@
gpio-key,wakeup;
};
};
amba {
mdma1: mdma@11C10000 {
/*
* MDMA1 can support both secure and non-secure
* AXI transactions. When this is enabled in the kernel
* for boards that run in secure mode, we are getting
* imprecise external aborts causing the kernel to oops.
*/
status = "disabled";
};
};
};

18
arch/arm/boot/dts/exynos5420.dtsi
View File

@ -264,16 +264,6 @@
reg = <0x100440C0 0x20>;
};
mau_pd: power-domain@100440E0 {
compatible = "samsung,exynos4210-pd";
reg = <0x100440E0 0x20>;
};
g2d_pd: power-domain@10044100 {
compatible = "samsung,exynos4210-pd";
reg = <0x10044100 0x20>;
};
msc_pd: power-domain@10044120 {
compatible = "samsung,exynos4210-pd";
reg = <0x10044120 0x20>;
@ -381,6 +371,13 @@
#dma-cells = <1>;
#dma-channels = <8>;
#dma-requests = <1>;
/*
* MDMA1 can support both secure and non-secure
* AXI transactions. When this is enabled in the kernel
* for boards that run in secure mode, we are getting
* imprecise external aborts causing the kernel to oops.
*/
status = "disabled";
};
};
@ -775,6 +772,5 @@
interrupts = <0 112 0>;
clocks = <&clock 471>;
clock-names = "secss";
samsung,power-domain = <&g2d_pd>;
};
};

1
arch/arm/configs/exynos_defconfig
View File

@ -65,6 +65,7 @@ CONFIG_TCG_TIS_I2C_INFINEON=y
CONFIG_I2C=y
CONFIG_I2C_MUX=y
CONFIG_I2C_ARB_GPIO_CHALLENGE=y
CONFIG_I2C_EXYNOS5=y
CONFIG_I2C_S3C2410=y
CONFIG_DEBUG_GPIO=y
# CONFIG_HWMON is not set

46
arch/arm/include/debug/s3c24xx.S Normal file
View File

@ -0,0 +1,46 @@
/* arch/arm/mach-s3c2410/include/mach/debug-macro.S
*
* Debugging macro include header
*
* Copyright (C) 1994-1999 Russell King
* Copyright (C) 2005 Simtec Electronics
*
* Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/serial_s3c.h>
#define S3C2410_UART1_OFF (0x4000)
.macro addruart, rp, rv, tmp
ldr \rp, = CONFIG_DEBUG_UART_PHYS
ldr \rv, = CONFIG_DEBUG_UART_VIRT
.endm
.macro fifo_full_s3c2410 rd, rx
ldr \rd, [\rx, # S3C2410_UFSTAT]
tst \rd, #S3C2410_UFSTAT_TXFULL
.endm
.macro fifo_level_s3c2410 rd, rx
ldr \rd, [\rx, # S3C2410_UFSTAT]
and \rd, \rd, #S3C2410_UFSTAT_TXMASK
.endm
/* Select the correct implementation depending on the configuration. The
* S3C2440 will get selected by default, as these are the most widely
* used variants of these
*/
#if defined(CONFIG_DEBUG_S3C2410_UART)
#define fifo_full fifo_full_s3c2410
#define fifo_level fifo_level_s3c2410
#endif
/* include the reset of the code which will do the work */
#include <debug/samsung.S>

92
arch/arm/mach-exynos/Kconfig
View File

@ -7,97 +7,102 @@
# Configuration options for the EXYNOS4
config ARCH_EXYNOS
bool "Samsung EXYNOS" if ARCH_MULTI_V7
select ARCH_HAS_BANDGAP
select ARCH_HAS_CPUFREQ
select ARCH_HAS_HOLES_MEMORYMODEL
select ARCH_REQUIRE_GPIOLIB
select ARM_AMBA
select ARM_GIC
select COMMON_CLK_SAMSUNG
select HAVE_ARM_SCU if SMP
select HAVE_S3C2410_I2C if I2C
select HAVE_S3C2410_WATCHDOG if WATCHDOG
select HAVE_S3C_RTC if RTC_CLASS
select PINCTRL
select PINCTRL_EXYNOS
select PM_GENERIC_DOMAINS if PM_RUNTIME
select S5P_DEV_MFC
select SRAM
help
Support for SAMSUNG EXYNOS SoCs (EXYNOS4/5)
if ARCH_EXYNOS
menu "SAMSUNG EXYNOS SoCs Support"
config ARCH_EXYNOS3
bool "SAMSUNG EXYNOS3"
select ARM_CPU_SUSPEND if PM
help
Samsung EXYNOS3 (Crotex-A7) SoC based systems
config ARCH_EXYNOS4
bool "SAMSUNG EXYNOS4"
default y
select ARM_AMBA
select CLKSRC_OF
select ARM_CPU_SUSPEND if PM_SLEEP
select CLKSRC_SAMSUNG_PWM if CPU_EXYNOS4210
select CPU_EXYNOS4210
select GIC_NON_BANKED
select KEYBOARD_SAMSUNG if INPUT_KEYBOARD
select HAVE_ARM_SCU if SMP
select HAVE_SMP
select MIGHT_HAVE_CACHE_L2X0
select PINCTRL
select PM_GENERIC_DOMAINS if PM_RUNTIME
select S5P_DEV_MFC
help
Samsung EXYNOS4 SoCs based systems
Samsung EXYNOS4 (Cortex-A9) SoC based systems
config ARCH_EXYNOS5
bool "SAMSUNG EXYNOS5"
select ARM_AMBA
select CLKSRC_OF
select HAVE_ARM_SCU if SMP
select HAVE_SMP
select PINCTRL
default y
help
Samsung EXYNOS5 (Cortex-A15) SoC based systems
Samsung EXYNOS5 (Cortex-A15/A7) SoC based systems
comment "EXYNOS SoCs"
config SOC_EXYNOS3250
bool "SAMSUNG EXYNOS3250"
default y
depends on ARCH_EXYNOS3
config CPU_EXYNOS4210
bool "SAMSUNG EXYNOS4210"
default y
depends on ARCH_EXYNOS4
select ARCH_HAS_BANDGAP
select ARM_CPU_SUSPEND if PM_SLEEP
select PINCTRL_EXYNOS
select SAMSUNG_DMADEV
help
Enable EXYNOS4210 CPU support
config SOC_EXYNOS4212
bool "SAMSUNG EXYNOS4212"
default y
depends on ARCH_EXYNOS4
select ARCH_HAS_BANDGAP
select PINCTRL_EXYNOS
select SAMSUNG_DMADEV
help
Enable EXYNOS4212 SoC support
config SOC_EXYNOS4412
bool "SAMSUNG EXYNOS4412"
default y
depends on ARCH_EXYNOS4
select ARCH_HAS_BANDGAP
select PINCTRL_EXYNOS
select SAMSUNG_DMADEV
help
Enable EXYNOS4412 SoC support
config SOC_EXYNOS5250
bool "SAMSUNG EXYNOS5250"
default y
depends on ARCH_EXYNOS5
select ARCH_HAS_BANDGAP
select PINCTRL_EXYNOS
select PM_GENERIC_DOMAINS if PM_RUNTIME
select S5P_DEV_MFC
select SAMSUNG_DMADEV
help
Enable EXYNOS5250 SoC support
config SOC_EXYNOS5260
bool "SAMSUNG EXYNOS5260"
default y
depends on ARCH_EXYNOS5
config SOC_EXYNOS5410
bool "SAMSUNG EXYNOS5410"
default y
depends on ARCH_EXYNOS5
config SOC_EXYNOS5420
bool "SAMSUNG EXYNOS5420"
default y
depends on ARCH_EXYNOS5
select PM_GENERIC_DOMAINS if PM_RUNTIME
help
Enable EXYNOS5420 SoC support
config SOC_EXYNOS5440
bool "SAMSUNG EXYNOS5440"
default y
depends on ARCH_EXYNOS5
select ARCH_DMA_ADDR_T_64BIT if ARM_LPAE
select ARCH_HAS_BANDGAP
select ARCH_HAS_OPP
select HAVE_ARM_ARCH_TIMER
select AUTO_ZRELADDR
@ -108,6 +113,11 @@ config SOC_EXYNOS5440
help
Enable EXYNOS5440 SoC support
config SOC_EXYNOS5800
bool "SAMSUNG EXYNOS5800"
default y
depends on SOC_EXYNOS5420
endmenu
config EXYNOS5420_MCPM

9
arch/arm/mach-exynos/Makefile
View File

@ -5,6 +5,8 @@
#
# Licensed under GPLv2
ccflags-$(CONFIG_ARCH_MULTIPLATFORM) += -I$(srctree)/$(src)/include -I$(srctree)/arch/arm/plat-samsung/include
obj-y :=
obj-m :=
obj-n :=
@ -12,20 +14,15 @@ obj- :=
# Core
obj-$(CONFIG_ARCH_EXYNOS) += exynos.o
obj-$(CONFIG_ARCH_EXYNOS) += exynos.o pmu.o exynos-smc.o firmware.o
obj-$(CONFIG_PM_SLEEP) += pm.o sleep.o
obj-$(CONFIG_PM_GENERIC_DOMAINS) += pm_domains.o
obj-$(CONFIG_ARCH_EXYNOS) += pmu.o
obj-$(CONFIG_SMP) += platsmp.o headsmp.o
obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
obj-$(CONFIG_ARCH_EXYNOS) += exynos-smc.o
obj-$(CONFIG_ARCH_EXYNOS) += firmware.o
plus_sec := $(call as-instr,.arch_extension sec,+sec)
AFLAGS_exynos-smc.o :=-Wa,-march=armv7-a$(plus_sec)

99
arch/arm/mach-exynos/common.h
View File

@ -15,6 +15,102 @@
#include <linux/reboot.h>
#include <linux/of.h>
#define EXYNOS3250_SOC_ID 0xE3472000
#define EXYNOS3_SOC_MASK 0xFFFFF000
#define EXYNOS4210_CPU_ID 0x43210000
#define EXYNOS4212_CPU_ID 0x43220000
#define EXYNOS4412_CPU_ID 0xE4412200
#define EXYNOS4_CPU_MASK 0xFFFE0000
#define EXYNOS5250_SOC_ID 0x43520000
#define EXYNOS5410_SOC_ID 0xE5410000
#define EXYNOS5420_SOC_ID 0xE5420000
#define EXYNOS5440_SOC_ID 0xE5440000
#define EXYNOS5800_SOC_ID 0xE5422000
#define EXYNOS5_SOC_MASK 0xFFFFF000
extern unsigned long samsung_cpu_id;
#define IS_SAMSUNG_CPU(name, id, mask) \
static inline int is_samsung_##name(void) \
{ \
return ((samsung_cpu_id & mask) == (id & mask)); \
}
IS_SAMSUNG_CPU(exynos3250, EXYNOS3250_SOC_ID, EXYNOS3_SOC_MASK)
IS_SAMSUNG_CPU(exynos4210, EXYNOS4210_CPU_ID, EXYNOS4_CPU_MASK)
IS_SAMSUNG_CPU(exynos4212, EXYNOS4212_CPU_ID, EXYNOS4_CPU_MASK)
IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK)
IS_SAMSUNG_CPU(exynos5250, EXYNOS5250_SOC_ID, EXYNOS5_SOC_MASK)
IS_SAMSUNG_CPU(exynos5410, EXYNOS5410_SOC_ID, EXYNOS5_SOC_MASK)
IS_SAMSUNG_CPU(exynos5420, EXYNOS5420_SOC_ID, EXYNOS5_SOC_MASK)
IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK)
IS_SAMSUNG_CPU(exynos5800, EXYNOS5800_SOC_ID, EXYNOS5_SOC_MASK)
#if defined(CONFIG_SOC_EXYNOS3250)
# define soc_is_exynos3250() is_samsung_exynos3250()
#else
# define soc_is_exynos3250() 0
#endif
#if defined(CONFIG_CPU_EXYNOS4210)
# define soc_is_exynos4210() is_samsung_exynos4210()
#else
# define soc_is_exynos4210() 0
#endif
#if defined(CONFIG_SOC_EXYNOS4212)
# define soc_is_exynos4212() is_samsung_exynos4212()
#else
# define soc_is_exynos4212() 0
#endif
#if defined(CONFIG_SOC_EXYNOS4412)
# define soc_is_exynos4412() is_samsung_exynos4412()
#else
# define soc_is_exynos4412() 0
#endif
#define EXYNOS4210_REV_0 (0x0)
#define EXYNOS4210_REV_1_0 (0x10)
#define EXYNOS4210_REV_1_1 (0x11)
#if defined(CONFIG_SOC_EXYNOS5250)
# define soc_is_exynos5250() is_samsung_exynos5250()
#else
# define soc_is_exynos5250() 0
#endif
#if defined(CONFIG_SOC_EXYNOS5410)
# define soc_is_exynos5410() is_samsung_exynos5410()
#else
# define soc_is_exynos5410() 0
#endif
#if defined(CONFIG_SOC_EXYNOS5420)
# define soc_is_exynos5420() is_samsung_exynos5420()
#else
# define soc_is_exynos5420() 0
#endif
#if defined(CONFIG_SOC_EXYNOS5440)
# define soc_is_exynos5440() is_samsung_exynos5440()
#else
# define soc_is_exynos5440() 0
#endif
#if defined(CONFIG_SOC_EXYNOS5800)
# define soc_is_exynos5800() is_samsung_exynos5800()
#else
# define soc_is_exynos5800() 0
#endif
#define soc_is_exynos4() (soc_is_exynos4210() || soc_is_exynos4212() || \
soc_is_exynos4412())
#define soc_is_exynos5() (soc_is_exynos5250() || soc_is_exynos5410() || \
soc_is_exynos5420() || soc_is_exynos5800())
void mct_init(void __iomem *base, int irq_g0, int irq_l0, int irq_l1);
struct map_desc;
@ -72,4 +168,7 @@ extern void exynos_cluster_power_up(int cluster);
extern int exynos_cluster_power_state(int cluster);
extern void exynos_enter_aftr(void);
extern void s5p_init_cpu(void __iomem *cpuid_addr);
extern unsigned int samsung_rev(void);
#endif /* __ARCH_ARM_MACH_EXYNOS_COMMON_H */

16
arch/arm/mach-exynos/exynos.c
View File

@ -26,8 +26,6 @@
#include <asm/mach/map.h>
#include <asm/memory.h>
#include <plat/cpu.h>
#include "common.h"
#include "mfc.h"
#include "regs-pmu.h"
@ -248,17 +246,6 @@ void __init exynos_init_io(void)
exynos_map_io();
}
struct bus_type exynos_subsys = {
.name = "exynos-core",
.dev_name = "exynos-core",
};
static int __init exynos_core_init(void)
{
return subsys_system_register(&exynos_subsys, NULL);
}
core_initcall(exynos_core_init);
static int __init exynos4_l2x0_cache_init(void)
{
int ret;
@ -310,12 +297,15 @@ static void __init exynos_dt_machine_init(void)
}
static char const *exynos_dt_compat[] __initconst = {
"samsung,exynos3",
"samsung,exynos3250",
"samsung,exynos4",
"samsung,exynos4210",
"samsung,exynos4212",
"samsung,exynos4412",
"samsung,exynos5",
"samsung,exynos5250",
"samsung,exynos5260",
"samsung,exynos5420",
"samsung,exynos5440",
NULL

20
arch/arm/mach-exynos/firmware.c
View File

@ -29,6 +29,21 @@ static int exynos_do_idle(void)
static int exynos_cpu_boot(int cpu)
{
/*
* Exynos3250 doesn't need to send smc command for secondary CPU boot
* because Exynos3250 removes WFE in secure mode.
*/
if (soc_is_exynos3250())
return 0;
/*
* The second parameter of SMC_CMD_CPU1BOOT command means CPU id.
* But, Exynos4212 has only one secondary CPU so second parameter
* isn't used for informing secure firmware about CPU id.
*/
if (soc_is_exynos4212())
cpu = 0;
exynos_smc(SMC_CMD_CPU1BOOT, cpu, 0, 0);
return 0;
}
@ -40,7 +55,10 @@ static int exynos_set_cpu_boot_addr(int cpu, unsigned long boot_addr)
if (!sysram_ns_base_addr)
return -ENODEV;
boot_reg = sysram_ns_base_addr + 0x1c + 4*cpu;
boot_reg = sysram_ns_base_addr + 0x1c;
if (!soc_is_exynos4212() && !soc_is_exynos3250())
boot_reg += 4*cpu;
__raw_writel(boot_addr, boot_reg);
return 0;

65
arch/arm/mach-exynos/hotplug.c
View File

@ -19,61 +19,9 @@
#include <asm/cp15.h>
#include <asm/smp_plat.h>
#include <plat/cpu.h>
#include "common.h"
#include "regs-pmu.h"
static inline void cpu_enter_lowpower_a9(void)
{
unsigned int v;
asm volatile(
" mcr p15, 0, %1, c7, c5, 0\n"
" mcr p15, 0, %1, c7, c10, 4\n"
/*
* Turn off coherency
*/
" mrc p15, 0, %0, c1, c0, 1\n"
" bic %0, %0, %3\n"
" mcr p15, 0, %0, c1, c0, 1\n"
" mrc p15, 0, %0, c1, c0, 0\n"
" bic %0, %0, %2\n"
" mcr p15, 0, %0, c1, c0, 0\n"
: "=&r" (v)
: "r" (0), "Ir" (CR_C), "Ir" (0x40)
: "cc");
}
static inline void cpu_enter_lowpower_a15(void)
{
unsigned int v;
asm volatile(
" mrc p15, 0, %0, c1, c0, 0\n"
" bic %0, %0, %1\n"
" mcr p15, 0, %0, c1, c0, 0\n"
: "=&r" (v)
: "Ir" (CR_C)
: "cc");
flush_cache_louis();
asm volatile(
/*
* Turn off coherency
*/
" mrc p15, 0, %0, c1, c0, 1\n"
" bic %0, %0, %1\n"
" mcr p15, 0, %0, c1, c0, 1\n"
: "=&r" (v)
: "Ir" (0x40)
: "cc");
isb();
dsb();
}
static inline void cpu_leave_lowpower(void)
{
unsigned int v;
@ -132,19 +80,8 @@ static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
void __ref exynos_cpu_die(unsigned int cpu)
{
int spurious = 0;
int primary_part = 0;
/*
* we're ready for shutdown now, so do it.
* Exynos4 is A9 based while Exynos5 is A15; check the CPU part
* number by reading the Main ID register and then perform the
* appropriate sequence for entering low power.
*/
asm("mrc p15, 0, %0, c0, c0, 0" : "=r"(primary_part) : : "cc");
if ((primary_part & 0xfff0) == 0xc0f0)
cpu_enter_lowpower_a15();
else
cpu_enter_lowpower_a9();
v7_exit_coherency_flush(louis);
platform_do_lowpower(cpu, &spurious);

4
arch/arm/mach-exynos/platsmp.c
View File

@ -27,8 +27,6 @@
#include <asm/smp_scu.h>
#include <asm/firmware.h>
#include <plat/cpu.h>
#include "common.h"
#include "regs-pmu.h"
@ -72,7 +70,7 @@ static inline void __iomem *cpu_boot_reg(int cpu)
return ERR_PTR(-ENODEV);
if (soc_is_exynos4412())
boot_reg += 4*cpu;
else if (soc_is_exynos5420())
else if (soc_is_exynos5420() || soc_is_exynos5800())
boot_reg += 4;
return boot_reg;
}

1
arch/arm/mach-exynos/pm.c
View File

@ -27,7 +27,6 @@
#include <asm/smp_scu.h>
#include <asm/suspend.h>
#include <plat/cpu.h>
#include <plat/pm-common.h>
#include <plat/pll.h>
#include <plat/regs-srom.h>

2
arch/arm/mach-exynos/pmu.c
View File

@ -13,8 +13,6 @@
#include <linux/kernel.h>
#include <linux/bug.h>
#include <plat/cpu.h>
#include "common.h"
#include "regs-pmu.h"

28
arch/arm/mach-s3c24xx/Kconfig
View File

@ -28,7 +28,6 @@ config CPU_S3C2410
bool "SAMSUNG S3C2410"
default y
select CPU_ARM920T
select CPU_LLSERIAL_S3C2410
select S3C2410_COMMON_CLK
select S3C2410_DMA if S3C24XX_DMA
select ARM_S3C2410_CPUFREQ if ARM_S3C24XX_CPUFREQ
@ -41,7 +40,6 @@ config CPU_S3C2410
config CPU_S3C2412
bool "SAMSUNG S3C2412"
select CPU_ARM926T
select CPU_LLSERIAL_S3C2440
select S3C2412_COMMON_CLK
select S3C2412_DMA if S3C24XX_DMA
select S3C2412_PM if PM
@ -51,7 +49,6 @@ config CPU_S3C2412
config CPU_S3C2416
bool "SAMSUNG S3C2416/S3C2450"
select CPU_ARM926T
select CPU_LLSERIAL_S3C2440
select S3C2416_PM if PM
select S3C2443_COMMON_CLK
select S3C2443_DMA if S3C24XX_DMA
@ -61,7 +58,6 @@ config CPU_S3C2416
config CPU_S3C2440
bool "SAMSUNG S3C2440"
select CPU_ARM920T
select CPU_LLSERIAL_S3C2440
select S3C2410_COMMON_CLK
select S3C2410_PM if PM
select S3C2440_DMA if S3C24XX_DMA
@ -71,7 +67,6 @@ config CPU_S3C2440
config CPU_S3C2442
bool "SAMSUNG S3C2442"
select CPU_ARM920T
select CPU_LLSERIAL_S3C2440
select S3C2410_COMMON_CLK
select S3C2410_DMA if S3C24XX_DMA
select S3C2410_PM if PM
@ -86,7 +81,6 @@ config CPU_S3C244X
config CPU_S3C2443
bool "SAMSUNG S3C2443"
select CPU_ARM920T
select CPU_LLSERIAL_S3C2440
select S3C2443_COMMON_CLK
select S3C2443_DMA if S3C24XX_DMA
help
@ -148,28 +142,6 @@ config S3C2410_PM
help
Power Management code common to S3C2410 and better
# low-level serial option nodes
config CPU_LLSERIAL_S3C2410_ONLY
bool
default y if CPU_LLSERIAL_S3C2410 && !CPU_LLSERIAL_S3C2440
config CPU_LLSERIAL_S3C2440_ONLY
bool
default y if CPU_LLSERIAL_S3C2440 && !CPU_LLSERIAL_S3C2410
config CPU_LLSERIAL_S3C2410
bool
help
Selected if there is an S3C2410 (or register compatible) serial
low-level implementation needed
config CPU_LLSERIAL_S3C2440
bool
help
Selected if there is an S3C2440 (or register compatible) serial
low-level implementation needed
config S3C24XX_PLL
bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
depends on ARM_S3C24XX_CPUFREQ

101
arch/arm/mach-s3c24xx/include/mach/debug-macro.S
View File

@ -1,101 +0,0 @@
/* arch/arm/mach-s3c2410/include/mach/debug-macro.S
*
* Debugging macro include header
*
* Copyright (C) 1994-1999 Russell King
* Copyright (C) 2005 Simtec Electronics
*
* Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <mach/map.h>
#include <mach/regs-gpio.h>
#include <linux/serial_s3c.h>
#define S3C2410_UART1_OFF (0x4000)
#define SHIFT_2440TXF (14-9)
.macro addruart, rp, rv, tmp
ldr \rp, = S3C24XX_PA_UART
ldr \rv, = S3C24XX_VA_UART
#if CONFIG_DEBUG_S3C_UART != 0
add \rp, \rp, #(S3C2410_UART1_OFF * CONFIG_DEBUG_S3C_UART)
add \rv, \rv, #(S3C2410_UART1_OFF * CONFIG_DEBUG_S3C_UART)
#endif
.endm
.macro fifo_full_s3c24xx rd, rx
@ check for arm920 vs arm926. currently assume all arm926
@ devices have an 64 byte FIFO identical to the s3c2440
mrc p15, 0, \rd, c0, c0
and \rd, \rd, #0xff0
teq \rd, #0x260
beq 1004f
mrc p15, 0, \rd, c1, c0
tst \rd, #1
addeq \rd, \rx, #(S3C24XX_PA_GPIO - S3C24XX_PA_UART)
addne \rd, \rx, #(S3C24XX_VA_GPIO - S3C24XX_VA_UART)
bic \rd, \rd, #0xff000
ldr \rd, [\rd, # S3C2410_GSTATUS1 - S3C2410_GPIOREG(0)]
and \rd, \rd, #0x00ff0000
teq \rd, #0x00440000 @ is it 2440?
1004:
ldr \rd, [\rx, # S3C2410_UFSTAT]
moveq \rd, \rd, lsr #SHIFT_2440TXF
tst \rd, #S3C2410_UFSTAT_TXFULL
.endm
.macro fifo_full_s3c2410 rd, rx
ldr \rd, [\rx, # S3C2410_UFSTAT]
tst \rd, #S3C2410_UFSTAT_TXFULL
.endm
/* fifo level reading */
.macro fifo_level_s3c24xx rd, rx
@ check for arm920 vs arm926. currently assume all arm926
@ devices have an 64 byte FIFO identical to the s3c2440
mrc p15, 0, \rd, c0, c0
and \rd, \rd, #0xff0
teq \rd, #0x260
beq 10000f
mrc p15, 0, \rd, c1, c0
tst \rd, #1
addeq \rd, \rx, #(S3C24XX_PA_GPIO - S3C24XX_PA_UART)
addne \rd, \rx, #(S3C24XX_VA_GPIO - S3C24XX_VA_UART)
bic \rd, \rd, #0xff000
ldr \rd, [\rd, # S3C2410_GSTATUS1 - S3C2410_GPIOREG(0)]
and \rd, \rd, #0x00ff0000
teq \rd, #0x00440000 @ is it 2440?
10000:
ldr \rd, [\rx, # S3C2410_UFSTAT]
andne \rd, \rd, #S3C2410_UFSTAT_TXMASK
andeq \rd, \rd, #S3C2440_UFSTAT_TXMASK
.endm
.macro fifo_level_s3c2410 rd, rx
ldr \rd, [\rx, # S3C2410_UFSTAT]
and \rd, \rd, #S3C2410_UFSTAT_TXMASK
.endm
/* Select the correct implementation depending on the configuration. The
* S3C2440 will get selected by default, as these are the most widely
* used variants of these
*/
#if defined(CONFIG_CPU_LLSERIAL_S3C2410_ONLY)
#define fifo_full fifo_full_s3c2410
#define fifo_level fifo_level_s3c2410
#elif !defined(CONFIG_CPU_LLSERIAL_S3C2440_ONLY)
#define fifo_full fifo_full_s3c24xx
#define fifo_level fifo_level_s3c24xx
#endif
/* include the reset of the code which will do the work */
#include <debug/samsung.S>

3
arch/arm/plat-samsung/Makefile
View File

@ -4,6 +4,9 @@
#
# Licensed under GPLv2
ccflags-$(CONFIG_ARCH_MULTI_V7) += -I$(srctree)/$(src)/include
ccflags-$(CONFIG_ARCH_EXYNOS) += -I$(srctree)/arch/arm/mach-exynos/include
obj-y :=
obj-m :=
obj-n := dummy.o

61
arch/arm/plat-samsung/include/plat/cpu.h
View File

@ -43,16 +43,6 @@ extern unsigned long samsung_cpu_id;
#define S5PV210_CPU_ID 0x43110000
#define S5PV210_CPU_MASK 0xFFFFF000
#define EXYNOS4210_CPU_ID 0x43210000
#define EXYNOS4212_CPU_ID 0x43220000
#define EXYNOS4412_CPU_ID 0xE4412200
#define EXYNOS4_CPU_MASK 0xFFFE0000
#define EXYNOS5250_SOC_ID 0x43520000
#define EXYNOS5420_SOC_ID 0xE5420000
#define EXYNOS5440_SOC_ID 0xE5440000
#define EXYNOS5_SOC_MASK 0xFFFFF000
#define IS_SAMSUNG_CPU(name, id, mask) \
static inline int is_samsung_##name(void) \
{ \
@ -68,12 +58,6 @@ IS_SAMSUNG_CPU(s5p6440, S5P6440_CPU_ID, S5P64XX_CPU_MASK)
IS_SAMSUNG_CPU(s5p6450, S5P6450_CPU_ID, S5P64XX_CPU_MASK)
IS_SAMSUNG_CPU(s5pc100, S5PC100_CPU_ID, S5PC100_CPU_MASK)
IS_SAMSUNG_CPU(s5pv210, S5PV210_CPU_ID, S5PV210_CPU_MASK)
IS_SAMSUNG_CPU(exynos4210, EXYNOS4210_CPU_ID, EXYNOS4_CPU_MASK)
IS_SAMSUNG_CPU(exynos4212, EXYNOS4212_CPU_ID, EXYNOS4_CPU_MASK)
IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK)
IS_SAMSUNG_CPU(exynos5250, EXYNOS5250_SOC_ID, EXYNOS5_SOC_MASK)
IS_SAMSUNG_CPU(exynos5420, EXYNOS5420_SOC_ID, EXYNOS5_SOC_MASK)
IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK)
#if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2412) || \
defined(CONFIG_CPU_S3C2416) || defined(CONFIG_CPU_S3C2440) || \
@ -126,50 +110,6 @@ IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK)
# define soc_is_s5pv210() 0
#endif
#if defined(CONFIG_CPU_EXYNOS4210)
# define soc_is_exynos4210() is_samsung_exynos4210()
#else
# define soc_is_exynos4210() 0
#endif
#if defined(CONFIG_SOC_EXYNOS4212)
# define soc_is_exynos4212() is_samsung_exynos4212()
#else
# define soc_is_exynos4212() 0
#endif
#if defined(CONFIG_SOC_EXYNOS4412)
# define soc_is_exynos4412() is_samsung_exynos4412()
#else
# define soc_is_exynos4412() 0
#endif
#define EXYNOS4210_REV_0 (0x0)
#define EXYNOS4210_REV_1_0 (0x10)
#define EXYNOS4210_REV_1_1 (0x11)
#if defined(CONFIG_SOC_EXYNOS5250)
# define soc_is_exynos5250() is_samsung_exynos5250()
#else
# define soc_is_exynos5250() 0
#endif
#if defined(CONFIG_SOC_EXYNOS5420)
# define soc_is_exynos5420() is_samsung_exynos5420()
#else
# define soc_is_exynos5420() 0
#endif
#if defined(CONFIG_SOC_EXYNOS5440)
# define soc_is_exynos5440() is_samsung_exynos5440()
#else
# define soc_is_exynos5440() 0
#endif
#define soc_is_exynos4() (soc_is_exynos4210() || soc_is_exynos4212() || \
soc_is_exynos4412())
#define soc_is_exynos5() (soc_is_exynos5250() || soc_is_exynos5420())
#define IODESC_ENT(x) { (unsigned long)S3C24XX_VA_##x, __phys_to_pfn(S3C24XX_PA_##x), S3C24XX_SZ_##x, MT_DEVICE }
#ifndef KHZ
@ -239,7 +179,6 @@ extern struct bus_type s3c2443_subsys;
extern struct bus_type s3c6410_subsys;
extern struct bus_type s5p64x0_subsys;
extern struct bus_type s5pv210_subsys;
extern struct bus_type exynos_subsys;
extern void (*s5pc1xx_idle)(void);

35
drivers/clk/samsung/clk-exynos5250.c
View File

@ -30,6 +30,8 @@
#define MPLL_CON0 0x4100
#define SRC_CORE1 0x4204
#define GATE_IP_ACP 0x8800
#define GATE_IP_ISP0 0xc800
#define GATE_IP_ISP1 0xc804
#define CPLL_LOCK 0x10020
#define EPLL_LOCK 0x10030
#define VPLL_LOCK 0x10040
@ -166,6 +168,8 @@ static unsigned long exynos5250_clk_regs[] __initdata = {
PLL_DIV2_SEL,
GATE_IP_DISP1,
GATE_IP_ACP,
GATE_IP_ISP0,
GATE_IP_ISP1,
};
static int exynos5250_clk_suspend(void)
@ -223,6 +227,7 @@ PNAME(mout_aclk400_p) = { "mout_aclk400_g3d_mid", "mout_gpll" };
PNAME(mout_aclk200_sub_p) = { "fin_pll", "div_aclk200" };
PNAME(mout_aclk266_sub_p) = { "fin_pll", "div_aclk266" };
PNAME(mout_aclk333_sub_p) = { "fin_pll", "div_aclk333" };
PNAME(mout_aclk400_isp_sub_p) = { "fin_pll", "div_aclk400_isp" };
PNAME(mout_hdmi_p) = { "div_hdmi_pixel", "sclk_hdmiphy" };
PNAME(mout_usb3_p) = { "mout_mpll_user", "mout_cpll" };
PNAME(mout_group1_p) = { "fin_pll", "fin_pll", "sclk_hdmi27m",
@ -302,6 +307,7 @@ static struct samsung_mux_clock exynos5250_mux_clks[] __initdata = {
MUX(0, "mout_aclk333", mout_aclk166_p, SRC_TOP0, 16, 1),
MUX(0, "mout_aclk400_g3d_mid", mout_aclk200_p, SRC_TOP0, 20, 1),
MUX(0, "mout_aclk400_isp", mout_aclk200_p, SRC_TOP1, 24, 1),
MUX(0, "mout_aclk400_g3d", mout_aclk400_p, SRC_TOP1, 28, 1),
MUX(0, "mout_cpll", mout_cpll_p, SRC_TOP2, 8, 1),
@ -313,6 +319,9 @@ static struct samsung_mux_clock exynos5250_mux_clks[] __initdata = {
MUX(0, "mout_aclk200_disp1_sub", mout_aclk200_sub_p, SRC_TOP3, 4, 1),
MUX(0, "mout_aclk266_gscl_sub", mout_aclk266_sub_p, SRC_TOP3, 8, 1),
MUX(0, "mout_aclk_266_isp_sub", mout_aclk266_sub_p, SRC_TOP3, 16, 1),
MUX(0, "mout_aclk_400_isp_sub", mout_aclk400_isp_sub_p,
SRC_TOP3, 20, 1),
MUX(0, "mout_aclk333_sub", mout_aclk333_sub_p, SRC_TOP3, 24, 1),
MUX(0, "mout_cam_bayer", mout_group1_p, SRC_GSCL, 12, 4),
@ -385,6 +394,7 @@ static struct samsung_div_clock exynos5250_div_clks[] __initdata = {
DIV(0, "div_aclk400_g3d", "mout_aclk400_g3d", DIV_TOP0,
24, 3),
DIV(0, "div_aclk400_isp", "mout_aclk400_isp", DIV_TOP1, 20, 3),
DIV(0, "div_aclk66_pre", "mout_mpll_user", DIV_TOP1, 24, 3),
DIV(0, "div_cam_bayer", "mout_cam_bayer", DIV_GSCL, 12, 4),
@ -650,6 +660,31 @@ static struct samsung_gate_clock exynos5250_gate_clks[] __initdata = {
GATE(CLK_WDT, "wdt", "div_aclk66", GATE_IP_PERIS, 19, 0, 0),
GATE(CLK_RTC, "rtc", "div_aclk66", GATE_IP_PERIS, 20, 0, 0),
GATE(CLK_TMU, "tmu", "div_aclk66", GATE_IP_PERIS, 21, 0, 0),
GATE(CLK_SMMU_TV, "smmu_tv", "mout_aclk200_disp1_sub",
GATE_IP_DISP1, 2, 0, 0),
GATE(CLK_SMMU_FIMD1, "smmu_fimd1", "mout_aclk200_disp1_sub",
GATE_IP_DISP1, 8, 0, 0),
GATE(CLK_SMMU_2D, "smmu_2d", "div_aclk200", GATE_IP_ACP, 7, 0, 0),
GATE(CLK_SMMU_FIMC_ISP, "smmu_fimc_isp", "mout_aclk_266_isp_sub",
GATE_IP_ISP0, 8, 0, 0),
GATE(CLK_SMMU_FIMC_DRC, "smmu_fimc_drc", "mout_aclk_266_isp_sub",
GATE_IP_ISP0, 9, 0, 0),
GATE(CLK_SMMU_FIMC_FD, "smmu_fimc_fd", "mout_aclk_266_isp_sub",
GATE_IP_ISP0, 10, 0, 0),
GATE(CLK_SMMU_FIMC_SCC, "smmu_fimc_scc", "mout_aclk_266_isp_sub",
GATE_IP_ISP0, 11, 0, 0),
GATE(CLK_SMMU_FIMC_SCP, "smmu_fimc_scp", "mout_aclk_266_isp_sub",
GATE_IP_ISP0, 12, 0, 0),
GATE(CLK_SMMU_FIMC_MCU, "smmu_fimc_mcu", "mout_aclk_400_isp_sub",
GATE_IP_ISP0, 13, 0, 0),
GATE(CLK_SMMU_FIMC_ODC, "smmu_fimc_odc", "mout_aclk_266_isp_sub",
GATE_IP_ISP1, 4, 0, 0),
GATE(CLK_SMMU_FIMC_DIS0, "smmu_fimc_dis0", "mout_aclk_266_isp_sub",
GATE_IP_ISP1, 5, 0, 0),
GATE(CLK_SMMU_FIMC_DIS1, "smmu_fimc_dis1", "mout_aclk_266_isp_sub",
GATE_IP_ISP1, 6, 0, 0),
GATE(CLK_SMMU_FIMC_3DNR, "smmu_fimc_3dnr", "mout_aclk_266_isp_sub",
GATE_IP_ISP1, 7, 0, 0),
};
static struct samsung_pll_rate_table vpll_24mhz_tbl[] __initdata = {

6
drivers/cpufreq/Kconfig.arm
View File

@ -30,7 +30,7 @@ config ARM_EXYNOS_CPUFREQ
config ARM_EXYNOS4210_CPUFREQ
bool "SAMSUNG EXYNOS4210"
depends on CPU_EXYNOS4210 && !ARCH_MULTIPLATFORM
depends on CPU_EXYNOS4210
default y
select ARM_EXYNOS_CPUFREQ
help
@ -41,7 +41,7 @@ config ARM_EXYNOS4210_CPUFREQ
config ARM_EXYNOS4X12_CPUFREQ
bool "SAMSUNG EXYNOS4x12"
depends on (SOC_EXYNOS4212 || SOC_EXYNOS4412) && !ARCH_MULTIPLATFORM
depends on SOC_EXYNOS4212 || SOC_EXYNOS4412
default y
select ARM_EXYNOS_CPUFREQ
help
@ -52,7 +52,7 @@ config ARM_EXYNOS4X12_CPUFREQ
config ARM_EXYNOS5250_CPUFREQ
bool "SAMSUNG EXYNOS5250"
depends on SOC_EXYNOS5250 && !ARCH_MULTIPLATFORM
depends on SOC_EXYNOS5250
default y
select ARM_EXYNOS_CPUFREQ
help

21
drivers/cpufreq/exynos-cpufreq.c
View File

@ -17,8 +17,7 @@
#include <linux/regulator/consumer.h>
#include <linux/cpufreq.h>
#include <linux/platform_device.h>
#include <plat/cpu.h>
#include <linux/of.h>
#include "exynos-cpufreq.h"
@ -163,14 +162,22 @@ static int exynos_cpufreq_probe(struct platform_device *pdev)
if (!exynos_info)
return -ENOMEM;
if (soc_is_exynos4210())
if (of_machine_is_compatible("samsung,exynos4210")) {
exynos_info->type = EXYNOS_SOC_4210;
ret = exynos4210_cpufreq_init(exynos_info);
else if (soc_is_exynos4212() || soc_is_exynos4412())
} else if (of_machine_is_compatible("samsung,exynos4212")) {
exynos_info->type = EXYNOS_SOC_4212;
ret = exynos4x12_cpufreq_init(exynos_info);
else if (soc_is_exynos5250())
} else if (of_machine_is_compatible("samsung,exynos4412")) {
exynos_info->type = EXYNOS_SOC_4412;
ret = exynos4x12_cpufreq_init(exynos_info);
} else if (of_machine_is_compatible("samsung,exynos5250")) {
exynos_info->type = EXYNOS_SOC_5250;
ret = exynos5250_cpufreq_init(exynos_info);
else
return 0;
} else {
pr_err("%s: Unknown SoC type\n", __func__);
return -ENODEV;
}
if (ret)
goto err_vdd_arm;

38
drivers/cpufreq/exynos-cpufreq.h
View File

@ -17,6 +17,13 @@ enum cpufreq_level_index {
L20,
};
enum exynos_soc_type {
EXYNOS_SOC_4210,
EXYNOS_SOC_4212,
EXYNOS_SOC_4412,
EXYNOS_SOC_5250,
};
#define APLL_FREQ(f, a0, a1, a2, a3, a4, a5, a6, a7, b0, b1, b2, m, p, s) \
{ \
.freq = (f) * 1000, \
@ -34,6 +41,7 @@ struct apll_freq {
};
struct exynos_dvfs_info {
enum exynos_soc_type type;
unsigned long mpll_freq_khz;
unsigned int pll_safe_idx;
struct clk *cpu_clk;
@ -41,6 +49,7 @@ struct exynos_dvfs_info {
struct cpufreq_frequency_table *freq_table;
void (*set_freq)(unsigned int, unsigned int);
bool (*need_apll_change)(unsigned int, unsigned int);
void __iomem *cmu_regs;
};
#ifdef CONFIG_ARM_EXYNOS4210_CPUFREQ
@ -68,24 +77,21 @@ static inline int exynos5250_cpufreq_init(struct exynos_dvfs_info *info)
}
#endif
#include <plat/cpu.h>
#include <mach/map.h>
#define EXYNOS4_CLKSRC_CPU 0x14200
#define EXYNOS4_CLKMUX_STATCPU 0x14400
#define EXYNOS4_CLKSRC_CPU (S5P_VA_CMU + 0x14200)
#define EXYNOS4_CLKMUX_STATCPU (S5P_VA_CMU + 0x14400)
#define EXYNOS4_CLKDIV_CPU (S5P_VA_CMU + 0x14500)
#define EXYNOS4_CLKDIV_CPU1 (S5P_VA_CMU + 0x14504)
#define EXYNOS4_CLKDIV_STATCPU (S5P_VA_CMU + 0x14600)
#define EXYNOS4_CLKDIV_STATCPU1 (S5P_VA_CMU + 0x14604)
#define EXYNOS4_CLKDIV_CPU 0x14500
#define EXYNOS4_CLKDIV_CPU1 0x14504
#define EXYNOS4_CLKDIV_STATCPU 0x14600
#define EXYNOS4_CLKDIV_STATCPU1 0x14604
#define EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT (16)
#define EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK (0x7 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT)
#define EXYNOS5_APLL_LOCK (S5P_VA_CMU + 0x00000)
#define EXYNOS5_APLL_CON0 (S5P_VA_CMU + 0x00100)
#define EXYNOS5_CLKMUX_STATCPU (S5P_VA_CMU + 0x00400)
#define EXYNOS5_CLKDIV_CPU0 (S5P_VA_CMU + 0x00500)
#define EXYNOS5_CLKDIV_CPU1 (S5P_VA_CMU + 0x00504)
#define EXYNOS5_CLKDIV_STATCPU0 (S5P_VA_CMU + 0x00600)
#define EXYNOS5_CLKDIV_STATCPU1 (S5P_VA_CMU + 0x00604)
#define EXYNOS5_APLL_LOCK 0x00000
#define EXYNOS5_APLL_CON0 0x00100
#define EXYNOS5_CLKMUX_STATCPU 0x00400
#define EXYNOS5_CLKDIV_CPU0 0x00500
#define EXYNOS5_CLKDIV_CPU1 0x00504
#define EXYNOS5_CLKDIV_STATCPU0 0x00600
#define EXYNOS5_CLKDIV_STATCPU1 0x00604

39
drivers/cpufreq/exynos4210-cpufreq.c
View File

@ -16,6 +16,8 @@
#include <linux/io.h>
#include <linux/slab.h>
#include <linux/cpufreq.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include "exynos-cpufreq.h"
@ -23,6 +25,7 @@ static struct clk *cpu_clk;
static struct clk *moutcore;
static struct clk *mout_mpll;
static struct clk *mout_apll;
static struct exynos_dvfs_info *cpufreq;
static unsigned int exynos4210_volt_table[] = {
1250000, 1150000, 1050000, 975000, 950000,
@ -60,20 +63,20 @@ static void exynos4210_set_clkdiv(unsigned int div_index)
tmp = apll_freq_4210[div_index].clk_div_cpu0;
__raw_writel(tmp, EXYNOS4_CLKDIV_CPU);
__raw_writel(tmp, cpufreq->cmu_regs + EXYNOS4_CLKDIV_CPU);
do {
tmp = __raw_readl(EXYNOS4_CLKDIV_STATCPU);
tmp = __raw_readl(cpufreq->cmu_regs + EXYNOS4_CLKDIV_STATCPU);
} while (tmp & 0x1111111);
/* Change Divider - CPU1 */
tmp = apll_freq_4210[div_index].clk_div_cpu1;
__raw_writel(tmp, EXYNOS4_CLKDIV_CPU1);
__raw_writel(tmp, cpufreq->cmu_regs + EXYNOS4_CLKDIV_CPU1);
do {
tmp = __raw_readl(EXYNOS4_CLKDIV_STATCPU1);
tmp = __raw_readl(cpufreq->cmu_regs + EXYNOS4_CLKDIV_STATCPU1);
} while (tmp & 0x11);
}
@ -85,7 +88,7 @@ static void exynos4210_set_apll(unsigned int index)
clk_set_parent(moutcore, mout_mpll);
do {
tmp = (__raw_readl(EXYNOS4_CLKMUX_STATCPU)
tmp = (__raw_readl(cpufreq->cmu_regs + EXYNOS4_CLKMUX_STATCPU)
>> EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT);
tmp &= 0x7;
} while (tmp != 0x2);
@ -96,7 +99,7 @@ static void exynos4210_set_apll(unsigned int index)
clk_set_parent(moutcore, mout_apll);
do {
tmp = __raw_readl(EXYNOS4_CLKMUX_STATCPU);
tmp = __raw_readl(cpufreq->cmu_regs + EXYNOS4_CLKMUX_STATCPU);
tmp &= EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK;
} while (tmp != (0x1 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT));
}
@ -115,8 +118,30 @@ static void exynos4210_set_frequency(unsigned int old_index,
int exynos4210_cpufreq_init(struct exynos_dvfs_info *info)
{
struct device_node *np;
unsigned long rate;
/*
* HACK: This is a temporary workaround to get access to clock
* controller registers directly and remove static mappings and
* dependencies on platform headers. It is necessary to enable
* Exynos multi-platform support and will be removed together with
* this whole driver as soon as Exynos gets migrated to use
* cpufreq-cpu0 driver.
*/
np = of_find_compatible_node(NULL, NULL, "samsung,exynos4210-clock");
if (!np) {
pr_err("%s: failed to find clock controller DT node\n",
__func__);
return -ENODEV;
}
info->cmu_regs = of_iomap(np, 0);
if (!info->cmu_regs) {
pr_err("%s: failed to map CMU registers\n", __func__);
return -EFAULT;
}
cpu_clk = clk_get(NULL, "armclk");
if (IS_ERR(cpu_clk))
return PTR_ERR(cpu_clk);
@ -143,6 +168,8 @@ int exynos4210_cpufreq_init(struct exynos_dvfs_info *info)
info->freq_table = exynos4210_freq_table;
info->set_freq = exynos4210_set_frequency;
cpufreq = info;
return 0;
err_mout_apll:

49
drivers/cpufreq/exynos4x12-cpufreq.c
View File

@ -16,6 +16,8 @@
#include <linux/io.h>
#include <linux/slab.h>
#include <linux/cpufreq.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include "exynos-cpufreq.h"
@ -23,6 +25,7 @@ static struct clk *cpu_clk;
static struct clk *moutcore;
static struct clk *mout_mpll;
static struct clk *mout_apll;
static struct exynos_dvfs_info *cpufreq;
static unsigned int exynos4x12_volt_table[] = {
1350000, 1287500, 1250000, 1187500, 1137500, 1087500, 1037500,
@ -100,28 +103,26 @@ static struct apll_freq apll_freq_4412[] = {
static void exynos4x12_set_clkdiv(unsigned int div_index)
{
unsigned int tmp;
unsigned int stat_cpu1;
/* Change Divider - CPU0 */
tmp = apll_freq_4x12[div_index].clk_div_cpu0;
__raw_writel(tmp, EXYNOS4_CLKDIV_CPU);
__raw_writel(tmp, cpufreq->cmu_regs + EXYNOS4_CLKDIV_CPU);
while (__raw_readl(EXYNOS4_CLKDIV_STATCPU) & 0x11111111)
while (__raw_readl(cpufreq->cmu_regs + EXYNOS4_CLKDIV_STATCPU)
& 0x11111111)
cpu_relax();
/* Change Divider - CPU1 */
tmp = apll_freq_4x12[div_index].clk_div_cpu1;
__raw_writel(tmp, EXYNOS4_CLKDIV_CPU1);
if (soc_is_exynos4212())
stat_cpu1 = 0x11;
else
stat_cpu1 = 0x111;
__raw_writel(tmp, cpufreq->cmu_regs + EXYNOS4_CLKDIV_CPU1);
while (__raw_readl(EXYNOS4_CLKDIV_STATCPU1) & stat_cpu1)
do {
cpu_relax();
tmp = __raw_readl(cpufreq->cmu_regs + EXYNOS4_CLKDIV_STATCPU1);
} while (tmp != 0x0);
}
static void exynos4x12_set_apll(unsigned int index)
@ -133,7 +134,7 @@ static void exynos4x12_set_apll(unsigned int index)
do {
cpu_relax();
tmp = (__raw_readl(EXYNOS4_CLKMUX_STATCPU)
tmp = (__raw_readl(cpufreq->cmu_regs + EXYNOS4_CLKMUX_STATCPU)
>> EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT);
tmp &= 0x7;
} while (tmp != 0x2);
@ -145,7 +146,7 @@ static void exynos4x12_set_apll(unsigned int index)
do {
cpu_relax();
tmp = __raw_readl(EXYNOS4_CLKMUX_STATCPU);
tmp = __raw_readl(cpufreq->cmu_regs + EXYNOS4_CLKMUX_STATCPU);
tmp &= EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK;
} while (tmp != (0x1 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT));
}
@ -164,8 +165,30 @@ static void exynos4x12_set_frequency(unsigned int old_index,
int exynos4x12_cpufreq_init(struct exynos_dvfs_info *info)
{
struct device_node *np;
unsigned long rate;
/*
* HACK: This is a temporary workaround to get access to clock
* controller registers directly and remove static mappings and
* dependencies on platform headers. It is necessary to enable
* Exynos multi-platform support and will be removed together with
* this whole driver as soon as Exynos gets migrated to use
* cpufreq-cpu0 driver.
*/
np = of_find_compatible_node(NULL, NULL, "samsung,exynos4412-clock");
if (!np) {
pr_err("%s: failed to find clock controller DT node\n",
__func__);
return -ENODEV;
}
info->cmu_regs = of_iomap(np, 0);
if (!info->cmu_regs) {
pr_err("%s: failed to map CMU registers\n", __func__);
return -EFAULT;
}
cpu_clk = clk_get(NULL, "armclk");
if (IS_ERR(cpu_clk))
return PTR_ERR(cpu_clk);
@ -184,7 +207,7 @@ int exynos4x12_cpufreq_init(struct exynos_dvfs_info *info)
if (IS_ERR(mout_apll))
goto err_mout_apll;
if (soc_is_exynos4212())
if (info->type == EXYNOS_SOC_4212)
apll_freq_4x12 = apll_freq_4212;
else
apll_freq_4x12 = apll_freq_4412;
@ -197,6 +220,8 @@ int exynos4x12_cpufreq_init(struct exynos_dvfs_info *info)
info->freq_table = exynos4x12_freq_table;
info->set_freq = exynos4x12_set_frequency;
cpufreq = info;
return 0;
err_mout_apll:

43
drivers/cpufreq/exynos5250-cpufreq.c
View File

@ -16,8 +16,8 @@
#include <linux/io.h>
#include <linux/slab.h>
#include <linux/cpufreq.h>
#include <mach/map.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include "exynos-cpufreq.h"
@ -25,6 +25,7 @@ static struct clk *cpu_clk;
static struct clk *moutcore;
static struct clk *mout_mpll;
static struct clk *mout_apll;
static struct exynos_dvfs_info *cpufreq;
static unsigned int exynos5250_volt_table[] = {
1300000, 1250000, 1225000, 1200000, 1150000,
@ -87,17 +88,18 @@ static void set_clkdiv(unsigned int div_index)
tmp = apll_freq_5250[div_index].clk_div_cpu0;
__raw_writel(tmp, EXYNOS5_CLKDIV_CPU0);
__raw_writel(tmp, cpufreq->cmu_regs + EXYNOS5_CLKDIV_CPU0);
while (__raw_readl(EXYNOS5_CLKDIV_STATCPU0) & 0x11111111)
while (__raw_readl(cpufreq->cmu_regs + EXYNOS5_CLKDIV_STATCPU0)
& 0x11111111)
cpu_relax();
/* Change Divider - CPU1 */
tmp = apll_freq_5250[div_index].clk_div_cpu1;
__raw_writel(tmp, EXYNOS5_CLKDIV_CPU1);
__raw_writel(tmp, cpufreq->cmu_regs + EXYNOS5_CLKDIV_CPU1);
while (__raw_readl(EXYNOS5_CLKDIV_STATCPU1) & 0x11)
while (__raw_readl(cpufreq->cmu_regs + EXYNOS5_CLKDIV_STATCPU1) & 0x11)
cpu_relax();
}
@ -111,7 +113,8 @@ static void set_apll(unsigned int index)
do {
cpu_relax();
tmp = (__raw_readl(EXYNOS5_CLKMUX_STATCPU) >> 16);
tmp = (__raw_readl(cpufreq->cmu_regs + EXYNOS5_CLKMUX_STATCPU)
>> 16);
tmp &= 0x7;
} while (tmp != 0x2);
@ -122,7 +125,7 @@ static void set_apll(unsigned int index)
do {
cpu_relax();
tmp = __raw_readl(EXYNOS5_CLKMUX_STATCPU);
tmp = __raw_readl(cpufreq->cmu_regs + EXYNOS5_CLKMUX_STATCPU);
tmp &= (0x7 << 16);
} while (tmp != (0x1 << 16));
}
@ -141,8 +144,30 @@ static void exynos5250_set_frequency(unsigned int old_index,
int exynos5250_cpufreq_init(struct exynos_dvfs_info *info)
{
struct device_node *np;
unsigned long rate;
/*
* HACK: This is a temporary workaround to get access to clock
* controller registers directly and remove static mappings and
* dependencies on platform headers. It is necessary to enable
* Exynos multi-platform support and will be removed together with
* this whole driver as soon as Exynos gets migrated to use
* cpufreq-cpu0 driver.
*/
np = of_find_compatible_node(NULL, NULL, "samsung,exynos5250-clock");
if (!np) {
pr_err("%s: failed to find clock controller DT node\n",
__func__);
return -ENODEV;
}
info->cmu_regs = of_iomap(np, 0);
if (!info->cmu_regs) {
pr_err("%s: failed to map CMU registers\n", __func__);
return -EFAULT;
}
cpu_clk = clk_get(NULL, "armclk");
if (IS_ERR(cpu_clk))
return PTR_ERR(cpu_clk);
@ -169,6 +194,8 @@ int exynos5250_cpufreq_init(struct exynos_dvfs_info *info)
info->freq_table = exynos5250_freq_table;
info->set_freq = exynos5250_set_frequency;
cpufreq = info;
return 0;
err_mout_apll:

16
include/dt-bindings/clock/exynos5250.h
View File

@ -152,6 +152,22 @@
#define CLK_SMMU_MDMA0 347
#define CLK_SSS 348
#define CLK_G3D 349
#define CLK_SMMU_TV 350
#define CLK_SMMU_FIMD1 351
#define CLK_SMMU_2D 352
#define CLK_SMMU_FIMC_ISP 353
#define CLK_SMMU_FIMC_DRC 354
#define CLK_SMMU_FIMC_SCC 355
#define CLK_SMMU_FIMC_SCP 356
#define CLK_SMMU_FIMC_FD 357
#define CLK_SMMU_FIMC_MCU 358
#define CLK_SMMU_FIMC_ODC 359
#define CLK_SMMU_FIMC_DIS0 360
#define CLK_SMMU_FIMC_DIS1 361
#define CLK_SMMU_FIMC_3DNR 362
#define CLK_SMMU_FIMC_LITE0 363
#define CLK_SMMU_FIMC_LITE1 364
#define CLK_CAMIF_TOP 365
/* mux clocks */
#define CLK_MOUT_HDMI 1024