ALSA: ice1712: Add Wolfson Microelectronics WM8766 codec support
Needed by Philips PSC724 subdriver. The code does not contain any card-specific bits so other ice17xx cards using this codec could be converted to use this generic code. Signed-off-by: Ondrej Zary <linux@rainbow-software.org> Signed-off-by: Takashi Iwai <tiwai@suse.de>
This commit is contained in:
Ondrej Zary
Takashi Iwai
parent
267bccaf04
commit
45d44e5a94
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/*
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* ALSA driver for ICEnsemble VT17xx
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*
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* Lowlevel functions for WM8766 codec
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*
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* Copyright (c) 2012 Ondrej Zary <linux@rainbow-software.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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*/
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#include <linux/delay.h>
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#include <sound/core.h>
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#include <sound/control.h>
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#include <sound/tlv.h>
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#include "wm8766.h"
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/* low-level access */
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static void snd_wm8766_write(struct snd_wm8766 *wm, u16 addr, u16 data)
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{
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if (addr < WM8766_REG_RESET)
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wm->regs[addr] = data;
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wm->ops.write(wm, addr, data);
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}
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/* mixer controls */
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static const DECLARE_TLV_DB_SCALE(wm8766_tlv, -12750, 50, 1);
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static struct snd_wm8766_ctl snd_wm8766_default_ctl[WM8766_CTL_COUNT] = {
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[WM8766_CTL_CH1_VOL] = {
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.name = "Channel 1 Playback Volume",
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.type = SNDRV_CTL_ELEM_TYPE_INTEGER,
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.tlv = wm8766_tlv,
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.reg1 = WM8766_REG_DACL1,
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.reg2 = WM8766_REG_DACR1,
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.mask1 = WM8766_VOL_MASK,
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.mask2 = WM8766_VOL_MASK,
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.max = 0xff,
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.flags = WM8766_FLAG_STEREO | WM8766_FLAG_VOL_UPDATE,
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},
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[WM8766_CTL_CH2_VOL] = {
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.name = "Channel 2 Playback Volume",
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.type = SNDRV_CTL_ELEM_TYPE_INTEGER,
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.tlv = wm8766_tlv,
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.reg1 = WM8766_REG_DACL2,
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.reg2 = WM8766_REG_DACR2,
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.mask1 = WM8766_VOL_MASK,
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.mask2 = WM8766_VOL_MASK,
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.max = 0xff,
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.flags = WM8766_FLAG_STEREO | WM8766_FLAG_VOL_UPDATE,
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},
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[WM8766_CTL_CH3_VOL] = {
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.name = "Channel 3 Playback Volume",
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.type = SNDRV_CTL_ELEM_TYPE_INTEGER,
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.tlv = wm8766_tlv,
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.reg1 = WM8766_REG_DACL3,
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.reg2 = WM8766_REG_DACR3,
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.mask1 = WM8766_VOL_MASK,
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.mask2 = WM8766_VOL_MASK,
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.max = 0xff,
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.flags = WM8766_FLAG_STEREO | WM8766_FLAG_VOL_UPDATE,
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},
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[WM8766_CTL_CH1_SW] = {
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.name = "Channel 1 Playback Switch",
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.type = SNDRV_CTL_ELEM_TYPE_BOOLEAN,
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.reg1 = WM8766_REG_DACCTRL2,
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.mask1 = WM8766_DAC2_MUTE1,
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.flags = WM8766_FLAG_INVERT,
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},
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[WM8766_CTL_CH2_SW] = {
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.name = "Channel 2 Playback Switch",
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.type = SNDRV_CTL_ELEM_TYPE_BOOLEAN,
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.reg1 = WM8766_REG_DACCTRL2,
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.mask1 = WM8766_DAC2_MUTE2,
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.flags = WM8766_FLAG_INVERT,
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},
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[WM8766_CTL_CH3_SW] = {
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.name = "Channel 3 Playback Switch",
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.type = SNDRV_CTL_ELEM_TYPE_BOOLEAN,
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.reg1 = WM8766_REG_DACCTRL2,
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.mask1 = WM8766_DAC2_MUTE3,
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.flags = WM8766_FLAG_INVERT,
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},
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[WM8766_CTL_PHASE1_SW] = {
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.name = "Channel 1 Phase Invert Playback Switch",
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.type = SNDRV_CTL_ELEM_TYPE_BOOLEAN,
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.reg1 = WM8766_REG_IFCTRL,
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.mask1 = WM8766_PHASE_INVERT1,
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},
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[WM8766_CTL_PHASE2_SW] = {
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.name = "Channel 2 Phase Invert Playback Switch",
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.type = SNDRV_CTL_ELEM_TYPE_BOOLEAN,
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.reg1 = WM8766_REG_IFCTRL,
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.mask1 = WM8766_PHASE_INVERT2,
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},
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[WM8766_CTL_PHASE3_SW] = {
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.name = "Channel 3 Phase Invert Playback Switch",
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.type = SNDRV_CTL_ELEM_TYPE_BOOLEAN,
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.reg1 = WM8766_REG_IFCTRL,
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.mask1 = WM8766_PHASE_INVERT3,
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},
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[WM8766_CTL_DEEMPH1_SW] = {
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.name = "Channel 1 Deemphasis Playback Switch",
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.type = SNDRV_CTL_ELEM_TYPE_BOOLEAN,
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.reg1 = WM8766_REG_DACCTRL2,
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.mask1 = WM8766_DAC2_DEEMP1,
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},
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[WM8766_CTL_DEEMPH2_SW] = {
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.name = "Channel 2 Deemphasis Playback Switch",
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.type = SNDRV_CTL_ELEM_TYPE_BOOLEAN,
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.reg1 = WM8766_REG_DACCTRL2,
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.mask1 = WM8766_DAC2_DEEMP2,
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},
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[WM8766_CTL_DEEMPH3_SW] = {
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.name = "Channel 3 Deemphasis Playback Switch",
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.type = SNDRV_CTL_ELEM_TYPE_BOOLEAN,
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.reg1 = WM8766_REG_DACCTRL2,
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.mask1 = WM8766_DAC2_DEEMP3,
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},
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[WM8766_CTL_IZD_SW] = {
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.name = "Infinite Zero Detect Playback Switch",
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.type = SNDRV_CTL_ELEM_TYPE_BOOLEAN,
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.reg1 = WM8766_REG_DACCTRL1,
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.mask1 = WM8766_DAC_IZD,
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},
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[WM8766_CTL_ZC_SW] = {
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.name = "Zero Cross Detect Playback Switch",
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.type = SNDRV_CTL_ELEM_TYPE_BOOLEAN,
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.reg1 = WM8766_REG_DACCTRL2,
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.mask1 = WM8766_DAC2_ZCD,
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.flags = WM8766_FLAG_INVERT,
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},
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};
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/* exported functions */
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void snd_wm8766_init(struct snd_wm8766 *wm)
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{
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int i;
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static const u16 default_values[] = {
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0x000, 0x100,
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0x120, 0x000,
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0x000, 0x100, 0x000, 0x100, 0x000,
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0x000, 0x080,
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};
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memcpy(wm->ctl, snd_wm8766_default_ctl, sizeof(wm->ctl));
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snd_wm8766_write(wm, WM8766_REG_RESET, 0x00); /* reset */
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udelay(10);
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/* load defaults */
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for (i = 0; i < ARRAY_SIZE(default_values); i++)
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snd_wm8766_write(wm, i, default_values[i]);
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}
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void snd_wm8766_resume(struct snd_wm8766 *wm)
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{
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int i;
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for (i = 0; i < WM8766_REG_COUNT; i++)
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snd_wm8766_write(wm, i, wm->regs[i]);
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}
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void snd_wm8766_set_if(struct snd_wm8766 *wm, u16 dac)
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{
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u16 val = wm->regs[WM8766_REG_IFCTRL] & ~WM8766_IF_MASK;
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dac &= WM8766_IF_MASK;
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snd_wm8766_write(wm, WM8766_REG_IFCTRL, val | dac);
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}
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void snd_wm8766_set_master_mode(struct snd_wm8766 *wm, u16 mode)
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{
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u16 val = wm->regs[WM8766_REG_DACCTRL3] & ~WM8766_DAC3_MSTR_MASK;
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mode &= WM8766_DAC3_MSTR_MASK;
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snd_wm8766_write(wm, WM8766_REG_DACCTRL3, val | mode);
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}
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void snd_wm8766_set_power(struct snd_wm8766 *wm, u16 power)
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{
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u16 val = wm->regs[WM8766_REG_DACCTRL3] & ~WM8766_DAC3_POWER_MASK;
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power &= WM8766_DAC3_POWER_MASK;
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snd_wm8766_write(wm, WM8766_REG_DACCTRL3, val | power);
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}
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void snd_wm8766_volume_restore(struct snd_wm8766 *wm)
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{
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u16 val = wm->regs[WM8766_REG_DACR1];
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/* restore volume after MCLK stopped */
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snd_wm8766_write(wm, WM8766_REG_DACR1, val | WM8766_VOL_UPDATE);
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}
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/* mixer callbacks */
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static int snd_wm8766_volume_info(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_info *uinfo)
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{
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struct snd_wm8766 *wm = snd_kcontrol_chip(kcontrol);
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int n = kcontrol->private_value;
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uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
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uinfo->count = (wm->ctl[n].flags & WM8766_FLAG_STEREO) ? 2 : 1;
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uinfo->value.integer.min = wm->ctl[n].min;
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uinfo->value.integer.max = wm->ctl[n].max;
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return 0;
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}
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static int snd_wm8766_enum_info(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_info *uinfo)
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{
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struct snd_wm8766 *wm = snd_kcontrol_chip(kcontrol);
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int n = kcontrol->private_value;
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return snd_ctl_enum_info(uinfo, 1, wm->ctl[n].max,
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wm->ctl[n].enum_names);
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}
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static int snd_wm8766_ctl_get(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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struct snd_wm8766 *wm = snd_kcontrol_chip(kcontrol);
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int n = kcontrol->private_value;
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u16 val1, val2;
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if (wm->ctl[n].get)
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wm->ctl[n].get(wm, &val1, &val2);
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else {
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val1 = wm->regs[wm->ctl[n].reg1] & wm->ctl[n].mask1;
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val1 >>= __ffs(wm->ctl[n].mask1);
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if (wm->ctl[n].flags & WM8766_FLAG_STEREO) {
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val2 = wm->regs[wm->ctl[n].reg2] & wm->ctl[n].mask2;
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val2 >>= __ffs(wm->ctl[n].mask2);
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if (wm->ctl[n].flags & WM8766_FLAG_VOL_UPDATE)
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val2 &= ~WM8766_VOL_UPDATE;
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}
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}
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if (wm->ctl[n].flags & WM8766_FLAG_INVERT) {
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val1 = wm->ctl[n].max - (val1 - wm->ctl[n].min);
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val2 = wm->ctl[n].max - (val2 - wm->ctl[n].min);
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}
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ucontrol->value.integer.value[0] = val1;
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if (wm->ctl[n].flags & WM8766_FLAG_STEREO)
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ucontrol->value.integer.value[1] = val2;
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return 0;
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}
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static int snd_wm8766_ctl_put(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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struct snd_wm8766 *wm = snd_kcontrol_chip(kcontrol);
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int n = kcontrol->private_value;
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u16 val, regval1, regval2;
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/* this also works for enum because value is an union */
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regval1 = ucontrol->value.integer.value[0];
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regval2 = ucontrol->value.integer.value[1];
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if (wm->ctl[n].flags & WM8766_FLAG_INVERT) {
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regval1 = wm->ctl[n].max - (regval1 - wm->ctl[n].min);
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regval2 = wm->ctl[n].max - (regval2 - wm->ctl[n].min);
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}
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if (wm->ctl[n].set)
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wm->ctl[n].set(wm, regval1, regval2);
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else {
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val = wm->regs[wm->ctl[n].reg1] & ~wm->ctl[n].mask1;
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val |= regval1 << __ffs(wm->ctl[n].mask1);
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/* both stereo controls in one register */
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if (wm->ctl[n].flags & WM8766_FLAG_STEREO &&
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wm->ctl[n].reg1 == wm->ctl[n].reg2) {
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val &= ~wm->ctl[n].mask2;
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val |= regval2 << __ffs(wm->ctl[n].mask2);
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}
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snd_wm8766_write(wm, wm->ctl[n].reg1, val);
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/* stereo controls in different registers */
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if (wm->ctl[n].flags & WM8766_FLAG_STEREO &&
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wm->ctl[n].reg1 != wm->ctl[n].reg2) {
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val = wm->regs[wm->ctl[n].reg2] & ~wm->ctl[n].mask2;
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val |= regval2 << __ffs(wm->ctl[n].mask2);
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if (wm->ctl[n].flags & WM8766_FLAG_VOL_UPDATE)
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val |= WM8766_VOL_UPDATE;
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snd_wm8766_write(wm, wm->ctl[n].reg2, val);
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}
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}
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return 0;
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}
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static int snd_wm8766_add_control(struct snd_wm8766 *wm, int num)
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{
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struct snd_kcontrol_new cont;
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struct snd_kcontrol *ctl;
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memset(&cont, 0, sizeof(cont));
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cont.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
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cont.private_value = num;
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cont.name = wm->ctl[num].name;
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cont.access = SNDRV_CTL_ELEM_ACCESS_READWRITE;
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if (wm->ctl[num].flags & WM8766_FLAG_LIM ||
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wm->ctl[num].flags & WM8766_FLAG_ALC)
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cont.access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
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cont.tlv.p = NULL;
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cont.get = snd_wm8766_ctl_get;
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cont.put = snd_wm8766_ctl_put;
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switch (wm->ctl[num].type) {
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case SNDRV_CTL_ELEM_TYPE_INTEGER:
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cont.info = snd_wm8766_volume_info;
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cont.access |= SNDRV_CTL_ELEM_ACCESS_TLV_READ;
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cont.tlv.p = wm->ctl[num].tlv;
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break;
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case SNDRV_CTL_ELEM_TYPE_BOOLEAN:
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wm->ctl[num].max = 1;
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if (wm->ctl[num].flags & WM8766_FLAG_STEREO)
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cont.info = snd_ctl_boolean_stereo_info;
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else
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cont.info = snd_ctl_boolean_mono_info;
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break;
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case SNDRV_CTL_ELEM_TYPE_ENUMERATED:
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cont.info = snd_wm8766_enum_info;
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break;
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default:
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return -EINVAL;
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}
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ctl = snd_ctl_new1(&cont, wm);
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if (!ctl)
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return -ENOMEM;
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wm->ctl[num].kctl = ctl;
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return snd_ctl_add(wm->card, ctl);
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}
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int snd_wm8766_build_controls(struct snd_wm8766 *wm)
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{
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int err, i;
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for (i = 0; i < WM8766_CTL_COUNT; i++)
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if (wm->ctl[i].name) {
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err = snd_wm8766_add_control(wm, i);
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if (err < 0)
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return err;
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}
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return 0;
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}
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@ -0,0 +1,163 @@
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#ifndef __SOUND_WM8766_H
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#define __SOUND_WM8766_H
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/*
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* ALSA driver for ICEnsemble VT17xx
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*
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* Lowlevel functions for WM8766 codec
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*
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* Copyright (c) 2012 Ondrej Zary <linux@rainbow-software.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
|
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*
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* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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*/
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#define WM8766_REG_DACL1 0x00
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#define WM8766_REG_DACR1 0x01
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#define WM8766_VOL_MASK 0x1ff /* incl. update bit */
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#define WM8766_VOL_UPDATE (1 << 8) /* update volume */
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#define WM8766_REG_DACCTRL1 0x02
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#define WM8766_DAC_MUTEALL (1 << 0)
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#define WM8766_DAC_DEEMPALL (1 << 1)
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#define WM8766_DAC_PDWN (1 << 2)
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#define WM8766_DAC_ATC (1 << 3)
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#define WM8766_DAC_IZD (1 << 4)
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#define WM8766_DAC_PL_MASK 0x1e0
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#define WM8766_DAC_PL_LL (1 << 5) /* L chan: L signal */
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#define WM8766_DAC_PL_LR (2 << 5) /* L chan: R signal */
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#define WM8766_DAC_PL_LB (3 << 5) /* L chan: both */
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#define WM8766_DAC_PL_RL (1 << 7) /* R chan: L signal */
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#define WM8766_DAC_PL_RR (2 << 7) /* R chan: R signal */
|
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#define WM8766_DAC_PL_RB (3 << 7) /* R chan: both */
|
||||
#define WM8766_REG_IFCTRL 0x03
|
||||
#define WM8766_IF_FMT_RIGHTJ (0 << 0)
|
||||
#define WM8766_IF_FMT_LEFTJ (1 << 0)
|
||||
#define WM8766_IF_FMT_I2S (2 << 0)
|
||||
#define WM8766_IF_FMT_DSP (3 << 0)
|
||||
#define WM8766_IF_DSP_LATE (1 << 2) /* in DSP mode */
|
||||
#define WM8766_IF_LRC_INVERTED (1 << 2) /* in other modes */
|
||||
#define WM8766_IF_BCLK_INVERTED (1 << 3)
|
||||
#define WM8766_IF_IWL_16BIT (0 << 4)
|
||||
#define WM8766_IF_IWL_20BIT (1 << 4)
|
||||
#define WM8766_IF_IWL_24BIT (2 << 4)
|
||||
#define WM8766_IF_IWL_32BIT (3 << 4)
|
||||
#define WM8766_IF_MASK 0x3f
|
||||
#define WM8766_PHASE_INVERT1 (1 << 6)
|
||||
#define WM8766_PHASE_INVERT2 (1 << 7)
|
||||
#define WM8766_PHASE_INVERT3 (1 << 8)
|
||||
#define WM8766_REG_DACL2 0x04
|
||||
#define WM8766_REG_DACR2 0x05
|
||||
#define WM8766_REG_DACL3 0x06
|
||||
#define WM8766_REG_DACR3 0x07
|
||||
#define WM8766_REG_MASTDA 0x08
|
||||
#define WM8766_REG_DACCTRL2 0x09
|
||||
#define WM8766_DAC2_ZCD (1 << 0)
|
||||
#define WM8766_DAC2_ZFLAG_ALL (0 << 1)
|
||||
#define WM8766_DAC2_ZFLAG_1 (1 << 1)
|
||||
#define WM8766_DAC2_ZFLAG_2 (2 << 1)
|
||||
#define WM8766_DAC2_ZFLAG_3 (3 << 1)
|
||||
#define WM8766_DAC2_MUTE1 (1 << 3)
|
||||
#define WM8766_DAC2_MUTE2 (1 << 4)
|
||||
#define WM8766_DAC2_MUTE3 (1 << 5)
|
||||
#define WM8766_DAC2_DEEMP1 (1 << 6)
|
||||
#define WM8766_DAC2_DEEMP2 (1 << 7)
|
||||
#define WM8766_DAC2_DEEMP3 (1 << 8)
|
||||
#define WM8766_REG_DACCTRL3 0x0a
|
||||
#define WM8766_DAC3_DACPD1 (1 << 1)
|
||||
#define WM8766_DAC3_DACPD2 (1 << 2)
|
||||
#define WM8766_DAC3_DACPD3 (1 << 3)
|
||||
#define WM8766_DAC3_PWRDNALL (1 << 4)
|
||||
#define WM8766_DAC3_POWER_MASK 0x1e
|
||||
#define WM8766_DAC3_MASTER (1 << 5)
|
||||
#define WM8766_DAC3_DAC128FS (0 << 6)
|
||||
#define WM8766_DAC3_DAC192FS (1 << 6)
|
||||
#define WM8766_DAC3_DAC256FS (2 << 6)
|
||||
#define WM8766_DAC3_DAC384FS (3 << 6)
|
||||
#define WM8766_DAC3_DAC512FS (4 << 6)
|
||||
#define WM8766_DAC3_DAC768FS (5 << 6)
|
||||
#define WM8766_DAC3_MSTR_MASK 0x1e0
|
||||
#define WM8766_REG_MUTE1 0x0c
|
||||
#define WM8766_MUTE1_MPD (1 << 6)
|
||||
#define WM8766_REG_MUTE2 0x0f
|
||||
#define WM8766_MUTE2_MPD (1 << 5)
|
||||
#define WM8766_REG_RESET 0x1f
|
||||
|
||||
#define WM8766_REG_COUNT 0x10 /* don't cache the RESET register */
|
||||
|
||||
struct snd_wm8766;
|
||||
|
||||
struct snd_wm8766_ops {
|
||||
void (*write)(struct snd_wm8766 *wm, u16 addr, u16 data);
|
||||
};
|
||||
|
||||
enum snd_wm8766_ctl_id {
|
||||
WM8766_CTL_CH1_VOL,
|
||||
WM8766_CTL_CH2_VOL,
|
||||
WM8766_CTL_CH3_VOL,
|
||||
WM8766_CTL_CH1_SW,
|
||||
WM8766_CTL_CH2_SW,
|
||||
WM8766_CTL_CH3_SW,
|
||||
WM8766_CTL_PHASE1_SW,
|
||||
WM8766_CTL_PHASE2_SW,
|
||||
WM8766_CTL_PHASE3_SW,
|
||||
WM8766_CTL_DEEMPH1_SW,
|
||||
WM8766_CTL_DEEMPH2_SW,
|
||||
WM8766_CTL_DEEMPH3_SW,
|
||||
WM8766_CTL_IZD_SW,
|
||||
WM8766_CTL_ZC_SW,
|
||||
|
||||
WM8766_CTL_COUNT,
|
||||
};
|
||||
|
||||
#define WM8766_ENUM_MAX 16
|
||||
|
||||
#define WM8766_FLAG_STEREO (1 << 0)
|
||||
#define WM8766_FLAG_VOL_UPDATE (1 << 1)
|
||||
#define WM8766_FLAG_INVERT (1 << 2)
|
||||
#define WM8766_FLAG_LIM (1 << 3)
|
||||
#define WM8766_FLAG_ALC (1 << 4)
|
||||
|
||||
struct snd_wm8766_ctl {
|
||||
struct snd_kcontrol *kctl;
|
||||
char *name;
|
||||
snd_ctl_elem_type_t type;
|
||||
const char *const enum_names[WM8766_ENUM_MAX];
|
||||
const unsigned int *tlv;
|
||||
u16 reg1, reg2, mask1, mask2, min, max, flags;
|
||||
void (*set)(struct snd_wm8766 *wm, u16 ch1, u16 ch2);
|
||||
void (*get)(struct snd_wm8766 *wm, u16 *ch1, u16 *ch2);
|
||||
};
|
||||
|
||||
enum snd_wm8766_agc_mode { WM8766_AGC_OFF, WM8766_AGC_LIM, WM8766_AGC_ALC };
|
||||
|
||||
struct snd_wm8766 {
|
||||
struct snd_card *card;
|
||||
struct snd_wm8766_ctl ctl[WM8766_CTL_COUNT];
|
||||
enum snd_wm8766_agc_mode agc_mode;
|
||||
struct snd_wm8766_ops ops;
|
||||
u16 regs[WM8766_REG_COUNT]; /* 9-bit registers */
|
||||
};
|
||||
|
||||
|
||||
|
||||
void snd_wm8766_init(struct snd_wm8766 *wm);
|
||||
void snd_wm8766_resume(struct snd_wm8766 *wm);
|
||||
void snd_wm8766_set_if(struct snd_wm8766 *wm, u16 dac);
|
||||
void snd_wm8766_set_master_mode(struct snd_wm8766 *wm, u16 mode);
|
||||
void snd_wm8766_set_power(struct snd_wm8766 *wm, u16 power);
|
||||
void snd_wm8766_volume_restore(struct snd_wm8766 *wm);
|
||||
int snd_wm8766_build_controls(struct snd_wm8766 *wm);
|
||||
|
||||
#endif /* __SOUND_WM8766_H */
|
||||
Loading…
Reference in New Issue