drm/i915: Cleanup South Error Interrupts
Cleanup and parametrize the handling of South Error Interrupts (SERR_INT). Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Mika Kahola <mika.kahola@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1507630626-23806-6-git-send-email-mika.kahola@intel.com
This commit is contained in:
parent
78619e32e5
commit
45c1cd8754
|
@ -2252,18 +2252,14 @@ static void ivb_err_int_handler(struct drm_i915_private *dev_priv)
|
|||
static void cpt_serr_int_handler(struct drm_i915_private *dev_priv)
|
||||
{
|
||||
u32 serr_int = I915_READ(SERR_INT);
|
||||
enum pipe pipe;
|
||||
|
||||
if (serr_int & SERR_INT_POISON)
|
||||
DRM_ERROR("PCH poison interrupt\n");
|
||||
|
||||
if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
|
||||
intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_A);
|
||||
|
||||
if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
|
||||
intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_B);
|
||||
|
||||
if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
|
||||
intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_C);
|
||||
for_each_pipe(dev_priv, pipe)
|
||||
if (serr_int & SERR_INT_TRANS_FIFO_UNDERRUN(pipe))
|
||||
intel_pch_fifo_underrun_irq_handler(dev_priv, pipe);
|
||||
|
||||
I915_WRITE(SERR_INT, serr_int);
|
||||
}
|
||||
|
|
|
@ -7182,9 +7182,6 @@ enum {
|
|||
|
||||
#define SERR_INT _MMIO(0xc4040)
|
||||
#define SERR_INT_POISON (1<<31)
|
||||
#define SERR_INT_TRANS_C_FIFO_UNDERRUN (1<<6)
|
||||
#define SERR_INT_TRANS_B_FIFO_UNDERRUN (1<<3)
|
||||
#define SERR_INT_TRANS_A_FIFO_UNDERRUN (1<<0)
|
||||
#define SERR_INT_TRANS_FIFO_UNDERRUN(pipe) (1<<((pipe)*3))
|
||||
|
||||
/* digital port hotplug */
|
||||
|
|
Loading…
Reference in New Issue