ARM: OMAP3: hwmod data: add HDQ/1-wire hwmod
Add the HDQ1W hwmod for OMAP34xx, OMAP36xx, and AM3505/3517 devices. According to the respective TRMs, it doesn't appear to be available for the 816x/814x or the AM335x. The OCPIF_SWSUP_IDLE flag is added to work around an apparent hardware bug: the hardware is not taking the CM_FCLKEN*_CORE.EN_HDQ bit into account when considering whether to go idle: http://www.spinics.net/lists/linux-omap/msg63576.html This causes HDQ transfers to fail or become corrupt. Thanks to NeilBrown for his help diagnosing and testing fixes for this problem. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: NeilBrown <neilb@suse.de> Tested-by: NeilBrown <neilb@suse.de>
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@ -1980,6 +1980,22 @@ static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = {
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},
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};
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static struct omap_hwmod omap3xxx_hdq1w_hwmod = {
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.name = "hdq1w",
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.mpu_irqs = omap2_hdq1w_mpu_irqs,
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.main_clk = "hdq_fck",
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.prcm = {
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.omap2 = {
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.module_offs = CORE_MOD,
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.prcm_reg_id = 1,
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.module_bit = OMAP3430_EN_HDQ_SHIFT,
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.idlest_reg_id = 1,
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.idlest_idle_bit = OMAP3430_ST_HDQ_SHIFT,
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},
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},
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.class = &omap2_hdq1w_class,
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};
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/*
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* interfaces
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*/
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@ -3059,6 +3075,16 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_tll_hs = {
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* l4_core -> hdq1w interface */
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static struct omap_hwmod_ocp_if omap3xxx_l4_core__hdq1w = {
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.master = &omap3xxx_l4_core_hwmod,
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.slave = &omap3xxx_hdq1w_hwmod,
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.clk = "hdq_ick",
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.addr = omap2_hdq1w_addr_space,
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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.flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
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};
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static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = {
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&omap3xxx_l3_main__l4_core,
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&omap3xxx_l3_main__l4_per,
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@ -3151,6 +3177,7 @@ static struct omap_hwmod_ocp_if *omap34xx_hwmod_ocp_ifs[] __initdata = {
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&omap34xx_l4_core__sr1,
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&omap34xx_l4_core__sr2,
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&omap3xxx_l4_core__mailbox,
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&omap3xxx_l4_core__hdq1w,
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NULL
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};
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@ -3170,6 +3197,7 @@ static struct omap_hwmod_ocp_if *omap36xx_hwmod_ocp_ifs[] __initdata = {
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&omap3xxx_l4_core__usb_tll_hs,
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&omap3xxx_l4_core__es3plus_mmc1,
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&omap3xxx_l4_core__es3plus_mmc2,
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&omap3xxx_l4_core__hdq1w,
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NULL
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};
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