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drm/i915: enable rc6 on ilk again 

I have the faint hope that the total absence of any locking for the
rps code wasn't too good an idea and could very well have caused some
rc6 related regressions.

Unfortunately we've never managed to reproduce these issues on any of
our own machines, so the only way to go about this is to enable it and
see what happens.

While at it, kill some stale comments and improve the logging.

Acked-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Daniel Vetter 2012-08-08 23:35:40 +02:00
parent 9270388e18
commit 456470eb58
1 changed files with 11 additions and 16 deletions
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27
drivers/gpu/drm/i915/intel_pm.c
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@ -2367,31 +2367,26 @@ static void gen6_disable_rps(struct drm_device *dev)
int intel_enable_rc6(const struct drm_device *dev) int intel_enable_rc6(const struct drm_device *dev)
{ {
/* /* Respect the kernel parameter if it is set */
* Respect the kernel parameter if it is set
*/
if (i915_enable_rc6 >= 0) if (i915_enable_rc6 >= 0)
return i915_enable_rc6; return i915_enable_rc6;
/* if (INTEL_INFO(dev)->gen == 5) {
* Disable RC6 on Ironlake DRM_DEBUG_DRIVER("Ironlake: only RC6 available\n");
*/
if (INTEL_INFO(dev)->gen == 5)
return 0;
/* On Haswell, only RC6 is available. So let's enable it by default to
* provide better testing and coverage since the beginning.
*/
if (IS_HASWELL(dev))
return INTEL_RC6_ENABLE; return INTEL_RC6_ENABLE;
}
/* if (IS_HASWELL(dev)) {
* Disable rc6 on Sandybridge DRM_DEBUG_DRIVER("Haswell: only RC6 available\n");
*/ return INTEL_RC6_ENABLE;
}
/* snb/ivb have more than one rc6 state. */
if (INTEL_INFO(dev)->gen == 6) { if (INTEL_INFO(dev)->gen == 6) {
DRM_DEBUG_DRIVER("Sandybridge: deep RC6 disabled\n"); DRM_DEBUG_DRIVER("Sandybridge: deep RC6 disabled\n");
return INTEL_RC6_ENABLE; return INTEL_RC6_ENABLE;
} }
DRM_DEBUG_DRIVER("RC6 and deep RC6 enabled\n"); DRM_DEBUG_DRIVER("RC6 and deep RC6 enabled\n");
return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE); return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
} }