drm/i915: Remove Braswell GGTT update w/a
Testing with concurrent GGTT accesses no longer show the coherency problems from yonder, commit5bab6f60cb
("drm/i915: Serialise updates to GGTT with access through GGTT on Braswell"). My presumption is that the root cause was more likely fixed by commit3b5724d702
("drm/i915: Wait for writes through the GTT to land before reading back"), along with the use of WC updates to the global gTT in commit8448661d65
("drm/i915: Convert clflushed pagetables over to WC maps". Given that the original symptoms can no longer be reproduced, time to remove the workaround. Testcase: igt/gem_concurrent_blit Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Link: http://patchwork.freedesktop.org/patch/msgid/20170220124718.14796-1-chris@chris-wilson.co.uk Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
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@ -2085,32 +2085,6 @@ static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
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ggtt->invalidate(vm->i915);
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}
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struct insert_entries {
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struct i915_address_space *vm;
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struct sg_table *st;
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u64 start;
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enum i915_cache_level level;
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u32 flags;
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};
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static int gen8_ggtt_insert_entries__cb(void *_arg)
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{
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struct insert_entries *arg = _arg;
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gen8_ggtt_insert_entries(arg->vm, arg->st,
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arg->start, arg->level, arg->flags);
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return 0;
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}
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static void gen8_ggtt_insert_entries__BKL(struct i915_address_space *vm,
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struct sg_table *st,
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u64 start,
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enum i915_cache_level level,
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u32 flags)
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{
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struct insert_entries arg = { vm, st, start, level, flags };
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stop_machine(gen8_ggtt_insert_entries__cb, &arg, NULL);
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}
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static void gen6_ggtt_insert_page(struct i915_address_space *vm,
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dma_addr_t addr,
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u64 offset,
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@ -2762,8 +2736,6 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
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ggtt->base.clear_range = gen8_ggtt_clear_range;
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ggtt->base.insert_entries = gen8_ggtt_insert_entries;
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if (IS_CHERRYVIEW(dev_priv))
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ggtt->base.insert_entries = gen8_ggtt_insert_entries__BKL;
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ggtt->invalidate = gen6_ggtt_invalidate;
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